{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,20]],"date-time":"2024-09-20T16:03:28Z","timestamp":1726848208978},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642328190"},{"type":"electronic","value":"9783642328206"}],"license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-32820-6_22","type":"book-chapter","created":{"date-parts":[[2012,8,23]],"date-time":"2012-08-23T12:26:25Z","timestamp":1345724785000},"page":"206-218","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols"],"prefix":"10.1007","author":[{"given":"Mario","family":"Lodde","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jose","family":"Flich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel E.","family":"Acacio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"22_CR1","unstructured":"Tile-gx processors family, \n                    \n                      http:\/\/www.tilera.com\/products\/TILE-Gx.php"},{"key":"22_CR2","unstructured":"Intel Core i7 technical Specifications, \n                    \n                      http:\/\/www.intel.com\/products\/processor\/corei7ee\/specifications.htm"},{"key":"22_CR3","doi-asserted-by":"crossref","unstructured":"Zhang, M., Asanovi\u0107, K.: Victim replication: Maximizing capacity while hiding wire delay in tiled chip multiprocessors. In: Proc. of the 32nd Int\u2019l Symposium on Computer Architecture (ISCA-32), pp. 336\u2013345 (2005)","DOI":"10.1145\/1080695.1069998"},{"key":"22_CR4","unstructured":"Li, L., Kadayif, I., Tsai, Y.-F., Vijaykrishnan, N., Kandemir, M., Irwin, M.J., Sivasubramaniam, A.: Leakage energy management in cache hierarchies. In: Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (2002)"},{"key":"22_CR5","doi-asserted-by":"crossref","unstructured":"Kaxiras, S., Hu, Z.: Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In: Proc. of the 28th Int\u2019l Symposium on Computer Architecture (ISCA 2001) (May 2001)","DOI":"10.1145\/379240.379268"},{"key":"22_CR6","doi-asserted-by":"crossref","unstructured":"Powell, M., Yang, S.-H., Falsafi, B., Roy, K., Vijaykumar, T.N.: Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories. In: Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2000 (2000)","DOI":"10.1145\/344166.344526"},{"key":"22_CR7","doi-asserted-by":"crossref","unstructured":"Miller, J.E., Kasture, H., Kurian, G., Gruenwald III, C., Beckmann, N., Celio, C., Eastep, J., Agarwal, A.: Graphite: A Distributed Parallel Simulator for Multicores. In: The 16th IEEE International Symposium on High-Performance Computer Architecture (HPCA) (January 2010)","DOI":"10.1109\/HPCA.2010.5416635"},{"key":"22_CR8","unstructured":"Cacti 5 Technical Report, \n                    \n                      http:\/\/www.hpl.hp.com\/techreports\/2008\/HPL-2008-20.html"},{"key":"22_CR9","doi-asserted-by":"crossref","unstructured":"Flautner, K., Kim, N.S., Martin, S., Blaauw, D., Mudge, T.: Drowsy caches: Simple techniques for reducing leakage power. In: Proceedings of the ACM\/IEEE 29th International Symposium on Computer Architecture, ISCA 2002 (2002)","DOI":"10.1145\/545214.545232"},{"key":"22_CR10","doi-asserted-by":"crossref","unstructured":"Kim, N.S., Flautner, K., Blaauw, D., Mudge, T.: Single-VDD and Single-VT super- drowsy techniques for low-leakage high-performance instruction caches. In: Proceedings of the ACM\/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2004 (2004)","DOI":"10.1145\/1013235.1013254"},{"key":"22_CR11","doi-asserted-by":"crossref","unstructured":"Abella, J., Gonzales, A., Vera, X., O\u2019Boule, M.F.P.: IATAC: A Smart Predictor to Turn-off L2 Cache Lines. ACM Transactions on Architecture and Code Optimization\u00a02(1) (March 2005)","DOI":"10.1145\/1061267.1061271"},{"key":"22_CR12","unstructured":"Drophso, S., Buyuktosunoglu, A., Balasubramonian, R., Albonesi, D.H., Dwarkadas, S., Semeraro, G., Magklis, G., Scott, M.L.: Integrating adaptive on-chip storage structures for reduced dynamic power. In: Proceedings of the IEEE 11th International Conference on Parallel Architectures and Compilation Techniques, PACT 2002 (2002)"},{"key":"22_CR13","doi-asserted-by":"crossref","unstructured":"Zhang, C., Vahid, F., Najjar, W.: A highly configurable cache architecture for embedded systems. In: Proceedings of the ACM\/IEEE 30th International Symposium on Computer Architecture, ISCA 2003 (2003)","DOI":"10.1145\/859618.859635"},{"key":"22_CR14","unstructured":"Moshovos, A., Memik, G., Falsafi, B., Choudhary, A.: Jetty: Filtering snoops for reduced energy consumption in SMP servers. In: Proceedings of International Symposium on High Performance Computer Architecture (HPCA 2001) (January 2001)"},{"key":"22_CR15","doi-asserted-by":"crossref","unstructured":"Salapura, V., Blumrich, M., Gara, A.: Design and implementation of the Blue Gene\/P snoop filter. In: Proceedings of International Symposium on High Performance Computer Architecture (HPCA 2007) (February 2007)","DOI":"10.1109\/HPCA.2008.4658623"},{"key":"22_CR16","doi-asserted-by":"crossref","unstructured":"Inoue, K., Ishihara, T., Muruami, K.: Way-predictive set-associative cache for high performance and low energy consumption. In: Proceedings of the ACM\/IEEE International Symposium on Low Power Electronics and Design, ISLPED 1999 (1999)","DOI":"10.1145\/313817.313948"},{"key":"22_CR17","unstructured":"Kin, J., Gupta, M., Mangione-Smith, W.-H.: The filter cache: An energy efficient memory structure. In: Proceedings of the ACM\/IEEE 30th International Symposium on Microarchitecture, MICRO 1997 (1997)"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2012 Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-32820-6_22","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,20]],"date-time":"2020-04-20T00:59:06Z","timestamp":1587344346000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-32820-6_22"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642328190","9783642328206"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-32820-6_22","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]},"assertion":[{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}