{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T09:24:15Z","timestamp":1725701055784},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642328190"},{"type":"electronic","value":"9783642328206"}],"license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-32820-6_24","type":"book-chapter","created":{"date-parts":[[2012,8,23]],"date-time":"2012-08-23T12:26:25Z","timestamp":1345724785000},"page":"232-245","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Exploiting Semantics of Virtual Memory to Improve the Efficiency of the On-Chip Memory System"],"prefix":"10.1007","author":[{"given":"Bin","family":"Li","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhen","family":"Fang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Li","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaowei","family":"Jiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lin","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew","family":"Herdrich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ravishankar","family":"Iyer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Srihari","family":"Makineni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"24_CR1","doi-asserted-by":"crossref","unstructured":"Romer, T.H., Ohlrich, W.H., Karlin, A.R., Bershad, B.N.: Reducing TLB and memory overhead using online superpage promotion. In: ISCA 1995, pp. 176\u2013187 (1995)","DOI":"10.1145\/225830.224419"},{"key":"24_CR2","doi-asserted-by":"crossref","unstructured":"McCurdy, C., Coxa, A.L., Vetter, J.: Investigating the TLB behavior of high-end scientific applications on commodity microprocessors. In: ISPASS 2008, pp. 95\u2013104 (2008)","DOI":"10.1109\/ISPASS.2008.4510742"},{"key":"24_CR3","doi-asserted-by":"crossref","unstructured":"Speight, E., Shafi, H., Zhang, L., Rajamony, R.: Adaptive mechanisms and policies for managing cache hierarchies in chip multiprocessors. In: ISCA 2005, pp. 346\u2013356 (2005)","DOI":"10.1145\/1080695.1069999"},{"key":"24_CR4","doi-asserted-by":"crossref","unstructured":"Muralimanohar, N., Balasubramonian, R., Jouppi, N.: Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0. In: MICRO, vol.\u00a040, pp. 3\u201314 (2007)","DOI":"10.1109\/MICRO.2007.33"},{"key":"24_CR5","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1109\/MM.2003.1179895","volume":"23","author":"H.S. Wang","year":"2003","unstructured":"Wang, H.S., Peh, L.S., Malik, S.: A power model for routers: Modeling Alpha 21364 and InfiniBand routers. IEEE Micro\u00a023, 26\u201335 (2003)","journal-title":"IEEE Micro"},{"key":"24_CR6","doi-asserted-by":"crossref","unstructured":"Lee, H.H.S., Ballapuram, C.S.: Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning. In: ISLPED 2003, pp. 306\u2013311 (2003)","DOI":"10.1145\/871506.871583"},{"key":"24_CR7","doi-asserted-by":"publisher","first-page":"21","DOI":"10.1109\/MM.2007.66","volume":"27","author":"L. Zhao","year":"2007","unstructured":"Zhao, L., Iyer, R., Moses, J., Illikkal, R., Makineni, S., Newell, D.: Exploring large-scale CMP architectures using ManySim. IEEE Micro\u00a027, 21\u201333 (2007)","journal-title":"IEEE Micro"},{"key":"24_CR8","doi-asserted-by":"crossref","unstructured":"Kahng, A., Li, B., Peh, L.-S., Samadi, K.: ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. In: DATE 2009, pp. 423\u2013428 (2009)","DOI":"10.1109\/DATE.2009.5090700"},{"key":"24_CR9","doi-asserted-by":"publisher","first-page":"89","DOI":"10.1145\/844128.844138","volume":"36","author":"J. Navarro","year":"2002","unstructured":"Navarro, J., Iyer, S., Druschel, P., Cox, A.: Practical, transparent operating system support for superpages. SIGOPS Oper. Syst. Rev.\u00a036, 89\u2013104 (2002)","journal-title":"SIGOPS Oper. Syst. Rev."},{"key":"24_CR10","unstructured":"Ganapathy, N., Schimmel, C.: General purpose operating system support for multiple page sizes. In: ATEC 1998 (1998)"},{"key":"24_CR11","unstructured":"Subramanian, I., Mather, C., Peterson, K., Raghunath, B.: Implementation of multiple pagesize support in HP-UX. In: ATEC 1998, p. 9 (1998)"},{"key":"24_CR12","doi-asserted-by":"crossref","unstructured":"Cascaval, C., Duesterwald, E., Sweeney, P.F., Wisniewski, R.W.: Multiple page size modeling and optimization. In: PaCT 2005, pp. 339\u2013349 (2005)","DOI":"10.1109\/PACT.2005.32"},{"key":"24_CR13","doi-asserted-by":"publisher","first-page":"104","DOI":"10.1145\/1531793.1531812","volume":"43","author":"D. Nellans","year":"2009","unstructured":"Nellans, D., Balasubramonian, R., Brunvand, E.: OS execution on multi-cores: is out-sourcing worthwhile? SIGOPS Oper. Syst. Rev.\u00a043, 104\u2013105 (2009)","journal-title":"SIGOPS Oper. Syst. Rev."},{"key":"24_CR14","doi-asserted-by":"crossref","unstructured":"Huang, M., Renau, J., Yoo, S.M., Torrellas, J.: L1 data cache decomposition for energy efficiency. In: ISLPED 2001, pp. 10\u201315 (2001)","DOI":"10.1145\/383082.383086"},{"key":"24_CR15","doi-asserted-by":"crossref","unstructured":"Ballapuram, C.S., Sharif, A., Lee, H.H.S.: Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors. In: ASLPED 2008 (2008)","DOI":"10.1145\/1346281.1346290"},{"key":"24_CR16","doi-asserted-by":"crossref","unstructured":"Cho, S., Jin, L.: Managing distributed, shared L2 caches through OS-level page allocation. In: MICRO 2006 (2006)","DOI":"10.1109\/MICRO.2006.31"},{"key":"24_CR17","doi-asserted-by":"crossref","unstructured":"Jin, L., Cho, S.: SOS: A software-oriented distributed shared cache management approach for chip multiprocessors. In: PaCT 2009, pp. 361\u2013371 (2009)","DOI":"10.1109\/PACT.2009.14"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2012 Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-32820-6_24","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,20]],"date-time":"2020-04-20T00:59:31Z","timestamp":1587344371000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-32820-6_24"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642328190","9783642328206"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-32820-6_24","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]},"assertion":[{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}