{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T00:02:24Z","timestamp":1740096144652,"version":"3.37.3"},"publisher-location":"Berlin, Heidelberg","reference-count":22,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642328190"},{"type":"electronic","value":"9783642328206"}],"license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-32820-6_73","type":"book-chapter","created":{"date-parts":[[2012,8,23]],"date-time":"2012-08-23T12:26:25Z","timestamp":1345724785000},"page":"741-752","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Cost-Effective Contention Avoidance in a CMP with Shared Memory Controllers"],"prefix":"10.1007","author":[{"given":"Samuel","family":"Rodrigo","sequence":"first","affiliation":[]},{"given":"Frank Olaf","family":"Sem-Jacobsen","sequence":"additional","affiliation":[]},{"given":"Herv\u00e9","family":"Tatenguem","sequence":"additional","affiliation":[]},{"given":"Tor","family":"Skeie","sequence":"additional","affiliation":[]},{"given":"Davide","family":"Bertozzi","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"issue":"3","key":"73_CR1","doi-asserted-by":"publisher","first-page":"451","DOI":"10.1145\/1555815.1555810","volume":"37","author":"D. Abts","year":"2009","unstructured":"Abts, D., Enright Jerger, N.D., Kim, J., Gibson, D., Lipasti, M.H.: Achieving predictable performance through better memory controller placement in many-core CMPs. ACM SIGARCH Computer Architecture News\u00a037(3), 451 (2009), \n                    \n                      http:\/\/portal.acm.org\/citation.cfm?doid=1555815.1555810","journal-title":"ACM SIGARCH Computer Architecture News"},{"doi-asserted-by":"crossref","unstructured":"van den Brand, J., Ciordas, C., Goossens, K., Basten, T.: Congestion-Controlled Best-Effort Communication for Networks-on-Chip. In: 2007 Design, Automation & Test in Europe Conference & Exhibition, pp. 1\u20136 (April 2007), \n                    \n                      http:\/\/ieeexplore.ieee.org\/lpdocs\/epic03\/wrapper.htm?arnumber=4211925","key":"73_CR2","DOI":"10.1109\/DATE.2007.364415"},{"unstructured":"Chen, G., Li, F., Son, S.W., Kandemir, M.: Application mapping for chip multiprocessors. In: Proceedings of the 45th Annual Conference on Design Automation - DAC 2008, p. 620 (2008), \n                    \n                      http:\/\/portal.acm.org\/citation.cfm?doid=1391469.1391628","key":"73_CR3"},{"unstructured":"Das, R., Mutlu, O., Kumar, A., Azimi, M.: Application-to-core mapping policies to reduce interference in on-chip networks. Tech. rep., SAFARI Technical Report No. 2011 (2011), \n                    \n                      http:\/\/www.ece.cmu.edu\/~omutlu\/pub\/interference-aware-noc-mapping-TR-SAFARI-2011-001.pdf","key":"73_CR4"},{"unstructured":"Das, R., Mutlu, O., Moscibroda, T., Das, C.R.: Application-aware prioritization mechanisms for on-chip networks. In: Proceedings of the 42nd Annual IEEE\/ACM International Symposium on Microarchitecture - Micro-42, p. 280 (2009), \n                    \n                      http:\/\/portal.acm.org\/citation.cfm?doid=1669112.1669150","key":"73_CR5"},{"doi-asserted-by":"crossref","unstructured":"Flich, J., Bertozzi, D.: Designing Network On-Chip Architectures in the Nanoscale Era. Chapman & Hall\/CRC (2010)","key":"73_CR6","DOI":"10.1201\/b10477"},{"key":"73_CR7","doi-asserted-by":"publisher","first-page":"165","DOI":"10.1109\/NOCS.2010.25","volume-title":"Proceedings of the 2010 Fourth ACM\/IEEE International Symposium on Networks-on-Chip, NOCS 2010","author":"F. Gilabert","year":"2010","unstructured":"Gilabert, F., G\u00f3mez, M.E., Medardoni, S., Bertozzi, D.: Improved utilization of noc channel bandwidth by switch replication for cost-effective multi-processor systems-on-chip. In: Proceedings of the 2010 Fourth ACM\/IEEE International Symposium on Networks-on-Chip, NOCS 2010, pp. 165\u2013172. IEEE Computer Society, Washington, DC (2010), \n                    \n                      http:\/\/dx.doi.org\/10.1109\/NOCS.2010.25"},{"doi-asserted-by":"crossref","unstructured":"Gratz, P., Grot, B., Keckler, S.W.: Regional congestion awareness for load balance in networks-on-chip. In: HPCA, pp. 203\u2013214. IEEE Computer Society (2008)","key":"73_CR8","DOI":"10.1109\/HPCA.2008.4658640"},{"unstructured":"Grot, B., Keckler, S.W., Mutlu, O.: Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip. In: Proceedings of the 42nd Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 268\u2013279. ACM (2009), \n                    \n                      http:\/\/portal.acm.org\/citation.cfm?id=1669149","key":"73_CR9"},{"issue":"1","key":"73_CR10","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1145\/1269899.1254886","volume":"35","author":"R. Iyer","year":"2007","unstructured":"Iyer, R., Zhao, L., Guo, F., Illikkal, R., Makineni, S., Newell, D., Solihin, Y., Hsu, L., Reinhardt, S.: QoS policies and architecture for cache\/memory in CMP platforms. ACM SIGMETRICS Performance Evaluation Review\u00a035(1), 25 (2007), \n                    \n                      http:\/\/portal.acm.org\/citation.cfm?doid=1269899.1254886","journal-title":"ACM SIGMETRICS Performance Evaluation Review"},{"key":"73_CR11","doi-asserted-by":"publisher","first-page":"849","DOI":"10.1145\/1146909.1147125","volume-title":"Proceedings of the 43rd Annual Design Automation Conference, DAC 2006","author":"M. Li","year":"2006","unstructured":"Li, M., Zeng, Q.-A., Jone, W.-B.: DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. In: Proceedings of the 43rd Annual Design Automation Conference, DAC 2006, pp. 849\u2013852. ACM, New York (2006), \n                    \n                      http:\/\/doi.acm.org\/10.1145\/1146909.1147125"},{"unstructured":"Marescaux, T., Rangevall, A., Nollet, V., Bartic, A., Corporaal, H.: Distributed congestion control for packet switched networks on chip. In: Proceedings of the International Conference of Parallel Computing: Current Future Issues of High-End Computing, vol.\u00a033, pp. 761\u2013768. Citeseer (2005), \n                    \n                      http:\/\/citeseerx.ist.psu.edu\/viewdoc\/download?doi=10.1.1.89.1586&amp;rep=rep1&amp;type=pdf","key":"73_CR12"},{"doi-asserted-by":"crossref","unstructured":"Mej\u00eda, A., Flich, J., Duato, J., Reinemo, S.A., Skeie, T.: Segment-based routing: An efficient fault-tolerant routing algorithm for meshes and tori. In: International Parallel and Distributed Processing Symposium, p. 84 (2006)","key":"73_CR13","DOI":"10.1109\/IPDPS.2006.1639341"},{"unstructured":"Multi2sim Wiki: SPLASH\u20132 execution commands., \n                    \n                      http:\/\/www.multi2sim.org\/wiki\/index.php5\/SPLASH2_Execution_Commands","key":"73_CR14"},{"unstructured":"NaNoC: NaNoC design platform, \n                    \n                      http:\/\/www.nanoc-project.eu","key":"73_CR15"},{"doi-asserted-by":"crossref","unstructured":"Roca, S., Flich, J., Silla, F., Duato, J.: VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks. In: International Conference on High Performance Computing (HiPC), pp. 1\u201312 (2010)","key":"73_CR16","DOI":"10.1109\/HIPC.2010.5713170"},{"doi-asserted-by":"crossref","unstructured":"Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho, J., Silla, F., Duato, J.: Addressing manufacturing challenges with cost-efficient fault tolerant routing. In: NOCS 2010: Proceedings of the 4th ACM\/IEEE International Symposium on Networks-on-Chip, pp. 25\u201332 (2010)","key":"73_CR17","DOI":"10.1109\/NOCS.2010.12"},{"issue":"1","key":"73_CR18","first-page":"4","volume":"7","author":"D. Sanchez","year":"2010","unstructured":"Sanchez, D., Michelogiannakis, G., Kozyrakis, C.: An analysis of on-chip interconnection networks for large-scale chip multiprocessors. ACM Transactions on Architecture and Code Optimization (TACO)\u00a07(1), 4 (2010), \n                    \n                      http:\/\/portal.acm.org\/citation.cfm?id=1736069","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"unstructured":"Thottethodi, M., Lebeck, A., Mukherjee, S.: Self-tuned congestion control for multiprocessor networks. In: The Seventh International Symposium on High-Performance Computer Architecture, HPCA, pp. 107\u2013118. IEEE (2001), \n                    \n                      http:\/\/ieeexplore.ieee.org\/xpls\/abs_all.jsp?arnumber=903256","key":"73_CR19"},{"issue":"2","key":"73_CR20","doi-asserted-by":"publisher","first-page":"230","DOI":"10.1016\/j.micpro.2010.10.001","volume":"35","author":"F. Trivi\u00f1o","year":"2011","unstructured":"Trivi\u00f1o, F., S\u00e1nchez, J.L., Alfaro, F.J., Flich, J.: Virtualizing network-on-chip resources in chip-multiprocessors. Microprocessors and Microsystems\u00a035(2), 230\u2013245 (2011), \n                    \n                      http:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0141933110000712","journal-title":"Microprocessors and Microsystems"},{"doi-asserted-by":"crossref","unstructured":"Ubal, R., Sahuquillo, J., Petit, S., L\u00f3pez, P.: Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. In: Proc. of the 19th Int\u2019l Symposium on Computer Architecture and High Performance Computing (2007)","key":"73_CR21","DOI":"10.1109\/SBAC-PAD.2007.17"},{"key":"73_CR22","doi-asserted-by":"publisher","first-page":"36","DOI":"10.1145\/1118299.1118310","volume-title":"Proceedings of the 2006 Asia and South Pacific Design Automation Conference, ASP-DAC 2006","author":"D. Wu","year":"2006","unstructured":"Wu, D., Al-Hashimi, B.M., Schmitz, M.T.: Improving routing efficiency for network-on-chip through contention-aware input selection. In: Proceedings of the 2006 Asia and South Pacific Design Automation Conference, ASP-DAC 2006, pp. 36\u201341. IEEE Press, Piscataway (2006), \n                    \n                      http:\/\/dx.doi.org\/10.1145\/1118299.1118310"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2012 Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-32820-6_73","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,20]],"date-time":"2020-04-20T00:56:30Z","timestamp":1587344190000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-32820-6_73"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642328190","9783642328206"],"references-count":22,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-32820-6_73","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]},"assertion":[{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}