{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T14:59:39Z","timestamp":1725893979873},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642330773"},{"type":"electronic","value":"9783642330780"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-33078-0_11","type":"book-chapter","created":{"date-parts":[[2012,9,3]],"date-time":"2012-09-03T17:37:49Z","timestamp":1346693869000},"page":"139-152","source":"Crossref","is-referenced-by-count":6,"title":["A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration"],"prefix":"10.1007","author":[{"given":"Yoshihiro","family":"Ichinomiya","sequence":"first","affiliation":[]},{"given":"Motoki","family":"Amagasaki","sequence":"additional","affiliation":[]},{"given":"Masahiro","family":"Iida","sequence":"additional","affiliation":[]},{"given":"Morihiro","family":"Kuga","sequence":"additional","affiliation":[]},{"given":"Toshinori","family":"Sueyoshi","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"11_CR1","unstructured":"Xilinx Inc., Partial Reconfiguration of Xilinx FPGAs Using ISE Design Suite, WP374(v1.1) (July 6, 2011)"},{"key":"11_CR2","unstructured":"Altera Inc., Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs, WP374(v1.1) (July 2010)"},{"key":"11_CR3","unstructured":"Xilinx Inc., Virtex-6 FPGA Configuration User Guide, UG360(v3.2) (2010)"},{"key":"11_CR4","doi-asserted-by":"crossref","unstructured":"Kalte, H., Porrmann, M.: REPLICA2Pro: Task relocation by bitstream manipulation in Virtex-II\/Pro FPGAs. In: Proceedings of the 3rd Conference on Computing Frontiers, pp. 403\u2013412 (2006)","DOI":"10.1145\/1128022.1128045"},{"key":"11_CR5","doi-asserted-by":"crossref","unstructured":"Corbetta, S., Morandi, M., Novati, M., Santambrogio, M.D., Sciuto, D., Spoletini, P.: Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems\u00a017(11) (November 2009)","DOI":"10.1109\/TVLSI.2008.2005670"},{"key":"11_CR6","doi-asserted-by":"crossref","unstructured":"Sudarsanam, A., Kallam, R., Dasu, A.: PRR-PRR Dynamic Relocation. IEEE Computer Architecture Letters\u00a08(2) (July-December 2009)","DOI":"10.1109\/L-CA.2009.49"},{"key":"11_CR7","doi-asserted-by":"crossref","unstructured":"Becker, T., Luk, W., Cheung, P.Y.K.: Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. In: 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines 2007, pp. 35\u201344 (April 2007)","DOI":"10.1109\/FCCM.2007.51"},{"key":"11_CR8","doi-asserted-by":"crossref","unstructured":"Montminy, D.P., Baldwin, R.O., Williams, P.D., Mullins, B.E.: Using Relocatable Bitstreams for Fault Tolerance. In: Second NASA\/ESA Conference on Adaptive Hardware and System 2007, pp. 701\u2013708 (August 2007)","DOI":"10.1109\/AHS.2007.108"},{"issue":"6","key":"11_CR9","doi-asserted-by":"publisher","first-page":"1048","DOI":"10.1109\/TVLSI.2010.2044902","volume":"19","author":"M. Koester","year":"2011","unstructured":"Koester, M., Luk, W., Hagemeyer, J., Porrmann, M., R\u00fcckert, U.: Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems\u00a019(6), 1048\u20131061 (2011)","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"11_CR10","unstructured":"Xilinx Inc., Constraints Guide, UG625 (v12.3) (September 21, 2010)"},{"key":"11_CR11","unstructured":"Xilinx Inc., PlanAhead Software Tutorial Partial Reconfiguration of a Processor Peripheral, UG744 (v13.2) (July 6, 2011)"},{"key":"11_CR12","unstructured":"Plasma - most MIPS(TM) opcode: Overview: Open-Cores, \n                    \n                      http:\/\/opencores.org\/project,plasma,overview"}],"container-title":["Lecture Notes in Computer Science","Algorithms and Architectures for Parallel Processing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-33078-0_11.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,4]],"date-time":"2021-05-04T07:54:22Z","timestamp":1620114862000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-33078-0_11"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642330773","9783642330780"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-33078-0_11","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]}}}