{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,20]],"date-time":"2025-04-20T01:40:02Z","timestamp":1745113202800,"version":"3.40.4"},"publisher-location":"Berlin, Heidelberg","reference-count":22,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642339400"},{"type":"electronic","value":"9783642339417"}],"license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-642-33941-7_27","type":"book-chapter","created":{"date-parts":[[2012,10,31]],"date-time":"2012-10-31T15:27:42Z","timestamp":1351697262000},"page":"295-308","source":"Crossref","is-referenced-by-count":2,"title":["Optimization of the Binary Adder Architectures Implemented in ASICs and FPGAs"],"prefix":"10.1007","author":[{"given":"Bojan","family":"Jovanovi\u0107","sequence":"first","affiliation":[]},{"given":"Milun","family":"Jevti\u0107","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"27_CR1","unstructured":"Fang, C., Huang, C., Wang, J., Yeh, C.: Fast and compact dynamic ripple carry adder design. In: IEEE Asia-Pacific Conf. on ASIC, pp. 25\u201328 (2002)"},{"key":"27_CR2","doi-asserted-by":"publisher","first-page":"340","DOI":"10.1109\/IRETELC.1962.5407919","volume":"11","author":"O. Bedrij","year":"1962","unstructured":"Bedrij, O.: Carry-select adder. IRE Trans. Electron. Comput.\u00a011, 340\u2013346 (1962)","journal-title":"IRE Trans. Electron. Comput."},{"key":"27_CR3","unstructured":"Alioto, M., Palumbo, G.: Optimized design of carry-bypass adders. In: European Conf. on Circuit Theory and Design, pp. 245\u2013248 (2001)"},{"key":"27_CR4","unstructured":"Chen, J.: Parallel-prefix structures for binary and modulo {2n-1,2n,2n+1} adders. PhD thesis, Oklahoma State University (2008)"},{"key":"27_CR5","unstructured":"Zimmermann, R.: Binary adder architectures for cell-based VLSI and their synthesis. PhD thesis, Swiss Federal Institute of Technology (1997)"},{"key":"27_CR6","doi-asserted-by":"publisher","first-page":"1162","DOI":"10.1109\/12.257703","volume":"42","author":"A. Tyagi","year":"1993","unstructured":"Tyagi, A.: A reduced area scheme for carry-select adders. IEEE Trans. Comput.\u00a042, 1162\u20131170 (1993)","journal-title":"IEEE Trans. Comput."},{"key":"27_CR7","unstructured":"Xilinx Inc., Virtex-6 FPGA data sheet: DC and Switching Characteristics, v3.4 edition (2012)"},{"key":"27_CR8","doi-asserted-by":"crossref","unstructured":"Jose, B., Radhakrishnan, D.: Delay optimized redundant binary adders. In: Int. Conf. on Electronics, Circuits and Systems, pp. 514\u2013517 (2006)","DOI":"10.1109\/ICECS.2006.379838"},{"key":"27_CR9","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1109\/92.988727","volume":"10","author":"A. Shams","year":"2002","unstructured":"Shams, A., Darwish, T., Bayoumi, M.: Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Trans. on VLSI Systems.\u00a010, 20\u201329 (2002)","journal-title":"IEEE Trans. on VLSI Systems."},{"key":"27_CR10","doi-asserted-by":"publisher","first-page":"686","DOI":"10.1109\/TVLSI.2005.848806","volume":"13","author":"C. Chang","year":"2005","unstructured":"Chang, C., Gu, J., Zhang, M.: A Review of 0.18 \/spl mu\/ m full adder performances for tree structured arithmetic circuits. IEEE Trans. on VLSI Systems\u00a013, 686\u2013695 (2005)","journal-title":"IEEE Trans. on VLSI Systems"},{"key":"27_CR11","doi-asserted-by":"publisher","first-page":"130","DOI":"10.1016\/j.mejo.2006.09.001","volume":"38","author":"M. Alioto","year":"2007","unstructured":"Alioto, M., Cataldo, G.D., Palumbo, G.: Mixed full adder topologies for high-performance low-power arithmetic circuits. Microelectronics Journal\u00a038, 130\u2013139 (2007)","journal-title":"Microelectronics Journal"},{"key":"27_CR12","unstructured":"Amelifard, B., Fallah, F., Pedram, M.: Closing the gap between carry select adder and ripple carry adder: a new class of low-power high performance adders. In: Int. Symp. on Quality of Electronic Design, pp. 148\u2013152 (2005)"},{"key":"27_CR13","doi-asserted-by":"crossref","unstructured":"Knowles, S.: A family of adders. In: 15th IEEE Symp. on Computer Arithmetic, pp. 277\u2013281 (2001)","DOI":"10.1109\/ARITH.2001.930129"},{"key":"27_CR14","unstructured":"Kharbash, F.: Redundant adder architectures, PhD Thesis, University of Missouri (2011)"},{"key":"27_CR15","doi-asserted-by":"crossref","unstructured":"Patil, D., Azizi, O., Horowitz, M., Ho, R.: Robust energy-efficient adder Topologies. In: 18th IEEE Symp. on Computer Arithmetic, pp. 16\u201328 (2007)","DOI":"10.1109\/ARITH.2007.31"},{"key":"27_CR16","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/54.655179","volume":"15","author":"X. Shanzen","year":"1998","unstructured":"Shanzen, X., Yu, W.: FPGA adders: performance evaluation and optimal design. IEEE Design&Test of Computers\u00a015, 24\u201329 (1998)","journal-title":"IEEE Design&Test of Computers"},{"key":"27_CR17","doi-asserted-by":"crossref","unstructured":"Dinechin, F., Nguyen, H., Pasca, B.: Pipelined FPGA adders. In: Int. Conf. on Field Programmable Logic, pp. 422\u2013427 (2010)","DOI":"10.1109\/FPL.2010.87"},{"key":"27_CR18","doi-asserted-by":"crossref","unstructured":"Nguyen, H., Pasca, B., Preusser, T.: FPGA-specific arithmetic optimizations of short-latency adders. In: Int. Conf. on Field Programmable Logic, pp. 232\u2013237 (2011)","DOI":"10.1109\/FPL.2011.49"},{"key":"27_CR19","doi-asserted-by":"crossref","unstructured":"Oklobdzija, V., Barnes, E.: Some optimal schemes for ALU implementation in VLSI technology. In: Proc. of the 7th Symposium on Comp. Arith., pp. 2\u20138 (1985)","DOI":"10.1109\/ARITH.1985.6158969"},{"key":"27_CR20","doi-asserted-by":"publisher","first-page":"226","DOI":"10.1109\/TEC.1960.5219822","volume":"9","author":"J. Sklansky","year":"1960","unstructured":"Sklansky, J.: Conditional sum addition logic. IRE Trans. on Electronic Computers\u00a09, 226\u2013231 (1960)","journal-title":"IRE Trans. on Electronic Computers"},{"key":"27_CR21","unstructured":"Jadhov, S.: Advanced computer arithmetic and computing. Technical Publications Pune (2009)"},{"key":"27_CR22","unstructured":"XPower Analyzer tutorial, ftp:\/\/ftp.xilinx.com\/pub\/documentation\/tutorials\/xpowerfpgatutorial.pdf"}],"container-title":["Advances in Intelligent Systems and Computing","Soft Computing Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-33941-7_27","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,20]],"date-time":"2025-04-20T01:08:27Z","timestamp":1745111307000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-642-33941-7_27"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783642339400","9783642339417"],"references-count":22,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-33941-7_27","relation":{},"ISSN":["2194-5357","2194-5365"],"issn-type":[{"type":"print","value":"2194-5357"},{"type":"electronic","value":"2194-5365"}],"subject":[],"published":{"date-parts":[[2013]]}}}