{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,8]],"date-time":"2025-04-08T04:28:57Z","timestamp":1744086537650,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642341342"},{"type":"electronic","value":"9783642341359"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-34135-9_22","type":"book-chapter","created":{"date-parts":[[2012,9,10]],"date-time":"2012-09-10T12:08:15Z","timestamp":1347278895000},"page":"215-224","source":"Crossref","is-referenced-by-count":0,"title":["Performance Analysis and Improvement Using LFSR in the Pipelined Key Scheduling Section of DES"],"prefix":"10.1007","author":[{"given":"P. V.","family":"Sruthi","sequence":"first","affiliation":[]},{"given":"Prabaharan","family":"Poornachandran","sequence":"additional","affiliation":[]},{"given":"A. S.","family":"Remya Ajai","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"22_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"151","DOI":"10.1007\/3-540-63465-7_220","volume-title":"Field Programmable Logic and Applications","author":"J. Leonard","year":"1997","unstructured":"Leonard, J., Mangione-Smith, W.H.: A Case Study of Partially Evaluated Hardware Circuits: Key-Specific DES. In: Glesner, M., Luk, W. (eds.) FPL 1997. LNCS, vol.\u00a01304, pp. 151\u2013160. Springer, Heidelberg (1997)"},{"key":"22_CR2","unstructured":"Van Der Lubbe, J.C.A.: Basic methods of cryptography. Cambridge University Press (1998)"},{"key":"22_CR3","unstructured":"Menezes, A., Oorschot, P., Vanstone, S.: Handbook of applied cryptography. CRC Press (1117)"},{"key":"22_CR4","doi-asserted-by":"publisher","first-page":"373","DOI":"10.1049\/ip-cds:20030574","volume":"150","author":"M. McLoone","year":"2003","unstructured":"McLoone, M., McCanny, J.: High-performance FPGA implementation of DES using a novel method for implementing the key schedule. IEE Proc.: Circuits, Devices & Systems\u00a0150, 373\u2013378 (2003)","journal-title":"IEE Proc.: Circuits, Devices & Systems"},{"key":"22_CR5","unstructured":"McLoone, M., McCanny, J.V.: Data encryption apparatus. UK Patent Application 0023409.6 (October 2000)"},{"key":"22_CR6","doi-asserted-by":"crossref","unstructured":"Wong, K., Wark, M., Dawson, E.: A single-chip FPGA implementation of the data encryption standard (DES) algorithm. In: Proc. IEEE Globecom Communications Conf., Sydney, Australia, pp. 827\u2013832 (November 1998)","DOI":"10.1109\/GLOCOM.1998.776849"},{"key":"22_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"260","DOI":"10.1007\/BFb0052352","volume-title":"Fast Software Encryption","author":"E. Biham","year":"1997","unstructured":"Biham, E.: A Fast New DES Implementation in Software. In: Biham, E. (ed.) FSE 1997. LNCS, vol.\u00a01267, pp. 260\u2013272. Springer, Heidelberg (1997)"},{"key":"22_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"234","DOI":"10.1007\/3-540-48892-8_19","volume-title":"Selected Areas in Cryptography","author":"J.-P. Kaps","year":"1999","unstructured":"Kaps, J.-P., Paar, C.: Fast DES Implementations for FPGAs and Its Application to a Universal Key-Search Machine. In: Tavares, S., Meijer, H. (eds.) SAC 1998. LNCS, vol.\u00a01556, pp. 234\u2013247. Springer, Heidelberg (1999)"},{"key":"22_CR9","unstructured":"Free-DES Core (March 2000), http:\/\/www.free-ip.com\/DES\/"},{"key":"22_CR10","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"37","DOI":"10.1007\/3-540-48059-5_5","volume-title":"Cryptographic Hardware and Embedded Systems","author":"D.C. Wilcox","year":"1999","unstructured":"Wilcox, D.C., Pierson, L.G., Robertson, P.J., Witzke, E.L., Gass, K.: A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond. In: Ko\u00e7, \u00c7.K., Paar, C. (eds.) CHES 1999. LNCS, vol.\u00a01717, pp. 37\u201348. Springer, Heidelberg (1999)"},{"key":"22_CR11","doi-asserted-by":"publisher","first-page":"113","DOI":"10.1109\/FPGA.2000.903398","volume-title":"Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, FC 2000","author":"C. Patterson","year":"2000","unstructured":"Patterson, C.: High performance DES encryption in virtex FPGAs using Jbits. In: Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, FC 2000, Napa Valley, CA, USA, pp. 113\u2013121. IEEE Comput. Soc., CA (2000)"},{"key":"22_CR12","unstructured":"Patel, V., Joshi, R.C., Saxena, A.K.: FPGA implementation of DES using pipelining Concept with skew core key-scheduling"}],"container-title":["Communications in Computer and Information Science","Recent Trends in Computer Networks and Distributed Systems Security"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-34135-9_22.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,8]],"date-time":"2025-04-08T02:30:09Z","timestamp":1744079409000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-34135-9_22"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642341342","9783642341359"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-34135-9_22","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2012]]}}}