{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:03:58Z","timestamp":1761581038514},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642354151"},{"type":"electronic","value":"9783642354168"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-35416-8_6","type":"book-chapter","created":{"date-parts":[[2012,11,15]],"date-time":"2012-11-15T03:35:58Z","timestamp":1352950558000},"page":"68-81","source":"Crossref","is-referenced-by-count":8,"title":["Three Phase Dynamic Current Mode Logic: A More Secure DyCML to Achieve a More Balanced Power Consumption"],"prefix":"10.1007","author":[{"given":"Hyunmin","family":"Kim","sequence":"first","affiliation":[]},{"given":"Vladimir","family":"Rozic","sequence":"additional","affiliation":[]},{"given":"Ingrid","family":"Verbauwhede","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"6_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"388","DOI":"10.1007\/3-540-48405-1_25","volume-title":"Advances in Cryptology - CRYPTO \u201999","author":"P.C. Kocher","year":"1999","unstructured":"Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol.\u00a01666, pp. 388\u2013397. Springer, Heidelberg (1999)"},{"key":"6_CR2","unstructured":"Tiri, K., Akmal, M., Verbauwhede, I.: A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards. In: ESSCIRC 2002, pp. 403\u2013406 (2002)"},{"key":"6_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"232","DOI":"10.1007\/11894063_19","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2006","author":"M. Bucci","year":"2006","unstructured":"Bucci, M., Giancane, L., Luzzi, R., Trifiletti, A.: Three-Phase Dual-Rail Pre-charge Logic. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol.\u00a04249, pp. 232\u2013241. Springer, Heidelberg (2006)"},{"key":"6_CR4","unstructured":"Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistanct ASIC of FPGA Implementation. In: DATE 2004, pp. 246\u2013251 (2004)"},{"key":"6_CR5","unstructured":"Mace, F., Standaert, F.X., Hassoune, I., Legat, J.D., Quisquater, J.J.: A Dynamic Current Mode Logic to Counteract Power Analysis Attacks. In: DCIS 2004, pp. 186\u2013191 (2004)"},{"issue":"1","key":"6_CR6","first-page":"54","volume":"36","author":"M. Yamashina","year":"1995","unstructured":"Yamashina, M., Yamada, H.: Mos current mode logic MCML circuit for low-power GHz processors. NEC Research Development\u00a036(1), 54\u201363 (1995)","journal-title":"NEC Research Development"},{"key":"6_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"230","DOI":"10.1007\/978-3-642-01004-0_13","volume-title":"Transactions on Computational Science IV","author":"F. Regazzoni","year":"2009","unstructured":"Regazzoni, F., Eisenbarth, T., Poschmann, A., Gro\u00dfsch\u00e4dl, J., Gurkaynak, F., Macchetti, M., Toprak, Z., Pozzi, L., Paar, C., Leblebici, Y., Ienne, P.: Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. In: Gavrilova, M.L., Tan, C.J.K., Moreno, E.D. (eds.) Trans. on Comput. Sci. IV. LNCS, vol.\u00a05430, pp. 230\u2013243. Springer, Heidelberg (2009)"},{"key":"6_CR8","doi-asserted-by":"crossref","unstructured":"Badel, S., Guleyupoglu, E., Inac, O., Martinez, A.P., Vietti, P., Gurkaynak, F., Leblebici, Y.: A generic standard cell design methodology for differential circuit styles. In: DATE 2008, pp. 843\u2013848 (2008)","DOI":"10.1109\/DATE.2008.4484779"},{"key":"6_CR9","doi-asserted-by":"publisher","first-page":"417","DOI":"10.1016\/j.vlsi.2004.07.014","volume":"38","author":"H. Hassan","year":"2005","unstructured":"Hassan, H., Anis, M., Elmasry, M.: Design and optimization of MOS current mode logic for parameter variations. VLSI Journal\u00a038, 417\u2013437 (2005)","journal-title":"VLSI Journal"},{"issue":"3","key":"6_CR10","doi-asserted-by":"publisher","first-page":"550","DOI":"10.1109\/4.910495","volume":"36","author":"M.W. Allam","year":"2001","unstructured":"Allam, M.W., Elmasry, M.: Dynamic Current Mode Logic(DyCML): A New Low-Power High-Performance Logic Style. IEEE Journal of Solid-State Circuits\u00a036(3), 550\u2013558 (2001)","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"5","key":"6_CR11","doi-asserted-by":"publisher","first-page":"1023","DOI":"10.1109\/TED.2010.2043389","volume":"57","author":"F. Ren","year":"2010","unstructured":"Ren, F., Markovic, D.: True energy-performance analysis of the MTJ-Based logic-in-memory architecture(1-bit full adder). IEEE Transactions on Electron Devices\u00a057(5), 1023\u20131028 (2010)","journal-title":"IEEE Transactions on Electron Devices"},{"key":"6_CR12","doi-asserted-by":"crossref","unstructured":"Sundstrom, J., Alvandpour, A.: A comparative analysis of logic styles for secure IC\u2019s against DPA attacks. In: NORCHIP 2005, pp. 297\u2013300 (2005)","DOI":"10.1109\/NORCHP.2005.1597048"},{"key":"6_CR13","doi-asserted-by":"crossref","unstructured":"Tiri, K., Verbauwhede, I.: Place and Route for Secure Standard Cell Design. In: CARDIS 2004, pp. 143\u2013158 (2004)","DOI":"10.1007\/1-4020-8147-2_10"},{"key":"6_CR14","doi-asserted-by":"crossref","unstructured":"Lin, L., Burleson, W.: Analysis and Mitigation of Process Variation impacts on Power-Analysis Tolerance. In: DAC 2009, pp. 238\u2013243 (2009)","DOI":"10.1145\/1629911.1629977"},{"key":"6_CR15","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"323","DOI":"10.1007\/978-3-540-30574-3_22","volume-title":"Topics in Cryptology \u2013 CT-RSA 2005","author":"N. Mentens","year":"2005","unstructured":"Mentens, N., Batina, L., Preneel, B., Verbauwhede, I.: A Systematic Evaluation of Compact Hardware Implementations for the Rijndael S-Box. In: Menezes, A. (ed.) CT-RSA 2005. LNCS, vol.\u00a03376, pp. 323\u2013333. Springer, Heidelberg (2005)"},{"key":"6_CR16","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"357","DOI":"10.1007\/978-3-540-28632-5_26","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2004","author":"M. Feldhofer","year":"2004","unstructured":"Feldhofer, M., Dominikus, S., Wolkerstorfer, J.: Strong Authentication for RFID Systems Using the AES Algorithm. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol.\u00a03156, pp. 357\u2013370. Springer, Heidelberg (2004)"}],"container-title":["Lecture Notes in Computer Science","Information Security Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-35416-8_6.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,4]],"date-time":"2021-05-04T13:15:20Z","timestamp":1620134120000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-35416-8_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642354151","9783642354168"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-35416-8_6","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]}}}