{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T13:37:34Z","timestamp":1725716254979},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642364235"},{"type":"electronic","value":"9783642364242"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-642-36424-2_24","type":"book-chapter","created":{"date-parts":[[2013,2,11]],"date-time":"2013-02-11T05:56:45Z","timestamp":1360562205000},"page":"280-291","source":"Crossref","is-referenced-by-count":0,"title":["HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation"],"prefix":"10.1007","author":[{"given":"Stefan","family":"Wallentowitz","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thomas","family":"Wild","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Herkersdorf","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"24_CR1","doi-asserted-by":"crossref","first-page":"1260","DOI":"10.1109\/DATE.2009.5090858","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2009","author":"C.H.K. Berkel van","year":"2009","unstructured":"van Berkel, C.H.K.: Multi-core for mobile phones. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2009, pp. 1260\u20131265. European Design and Automation Association, Leuven (2009)"},{"key":"24_CR2","doi-asserted-by":"crossref","unstructured":"Langendoen, K., et al.: Integrating Polling, Interrupts, and Thread Management. In: Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation, pp. 13\u201322. IEEE Computer Society (1996)","DOI":"10.1109\/FMPC.1996.558057"},{"key":"24_CR3","doi-asserted-by":"crossref","unstructured":"Goglin, B., Furmento, N.: Finding a tradeoff between host interrupt load and MPI latency over Ethernet. In: IEEE International Conference on Cluster Computing and Workshops, CLUSTER 2009, August 31-September 4, pp. 1\u20139 (2009)","DOI":"10.1109\/CLUSTR.2009.5289165"},{"key":"24_CR4","doi-asserted-by":"crossref","unstructured":"Kariniemi, H., Nurmi, J.: High-performance NoC Interface with interrupt batching for Micronmesh MPSoC prototype platform on FPGA. In: NORCHIP, pp. 1\u20136 (November 2010)","DOI":"10.1109\/NORCHIP.2010.5669449"},{"key":"24_CR5","doi-asserted-by":"publisher","first-page":"587","DOI":"10.1145\/1687399.1687508","volume-title":"Proceedings of the 2009 International Conference on Computer-Aided Design, ICCAD 2009","author":"J. Castrillon","year":"2009","unstructured":"Castrillon, J., et al.: Task management in MPSoCs: an ASIP approach. In: Proceedings of the 2009 International Conference on Computer-Aided Design, ICCAD 2009, pp. 587\u2013594. ACM, New York (2009)"},{"key":"24_CR6","doi-asserted-by":"publisher","first-page":"167","DOI":"10.1145\/1629395.1629419","volume-title":"Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009","author":"F. Scheler","year":"2009","unstructured":"Scheler, F., et al.: Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system. In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, pp. 167\u2013174. ACM, New York (2009)"},{"key":"24_CR7","doi-asserted-by":"crossref","unstructured":"N\u00e1cul, A.C., Regazzoni, F., Lajolo, M.: Hardware scheduling support in SMP architectures. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2007, San Jose, CA, USA, EDA Consortium, pp. 642\u2013647 (2007)","DOI":"10.1109\/DATE.2007.364666"},{"issue":"5","key":"24_CR8","doi-asserted-by":"publisher","first-page":"309","DOI":"10.1049\/ip-cdt:19960788","volume":"143","author":"A. Bolychevsky","year":"1996","unstructured":"Bolychevsky, A., Jesshope, C., Muchnick, V.: Dynamic scheduling in RISC architectures. IEE Proceedings Computers and Digital Techniques\u00a0143(5), 309\u2013317 (1996)","journal-title":"IEE Proceedings Computers and Digital Techniques"},{"key":"24_CR9","doi-asserted-by":"publisher","first-page":"149","DOI":"10.1016\/j.sysarc.2008.07.001","volume":"55","author":"K. Bousias","year":"2009","unstructured":"Bousias, K., et al.: Implementation and evaluation of a microthread architecture. J. Syst. Archit.\u00a055, 149\u2013161 (2009)","journal-title":"J. Syst. Archit."},{"key":"24_CR10","doi-asserted-by":"crossref","unstructured":"Hicks, M., van Tol, M., Jesshope, C.: Towards scalable I\/O on a many-core architecture. In: 2010 International Conference on Embedded Computer Systems (SAMOS), pp. 341\u2013348 (July 2010)","DOI":"10.1109\/ICSAMOS.2010.5642045"},{"key":"24_CR11","unstructured":"INMOS Limited: Transputer Reference Manual. Prentice Hall (1992)"}],"container-title":["Lecture Notes in Computer Science","Architecture of Computing Systems \u2013 ARCS 2013"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-36424-2_24","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,1,18]],"date-time":"2019-01-18T08:10:53Z","timestamp":1547799053000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-36424-2_24"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783642364235","9783642364242"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-36424-2_24","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2013]]}}}