{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T04:04:57Z","timestamp":1746072297813,"version":"3.40.4"},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642376573"},{"type":"electronic","value":"9783642376580"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-642-37658-0_9","type":"book-chapter","created":{"date-parts":[[2013,4,5]],"date-time":"2013-04-05T10:20:22Z","timestamp":1365157222000},"page":"127-142","source":"Crossref","is-referenced-by-count":0,"title":["UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores"],"prefix":"10.1007","author":[{"given":"Vasileios","family":"Porpodas","sequence":"first","affiliation":[]},{"given":"Marcelo","family":"Cintra","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"9_CR1","unstructured":"Gcc: Gnu compiler collection, http:\/\/gcc.gnu.org"},{"key":"9_CR2","doi-asserted-by":"crossref","unstructured":"Aleta, A., Codina, J., Gonz\u00e1lez, A., Kaeli, D.: Heterogeneous clustered vliw microarchitectures. In: CGO, pp. 354\u2013366 (2007)","DOI":"10.1109\/CGO.2007.15"},{"key":"9_CR3","doi-asserted-by":"crossref","unstructured":"Baniasadi, A., Moshovos, A.: Asymmetric-frequency clustering: a power-aware back-end for high-performance processors. In: ISLPED, pp. 255\u2013258 (2002)","DOI":"10.1109\/LPE.2002.146749"},{"key":"9_CR4","unstructured":"Desoli, G.: Instruction assignment for clustered vliw dsp compilers: A new approach. HP laboratories Technical Report HPL (1998)"},{"key":"9_CR5","unstructured":"Ellis, J.: Bulldog: A compiler for vliw architectures. Technical Report, Yale Univ., New Haven, CT, USA (1985)"},{"key":"9_CR6","doi-asserted-by":"crossref","unstructured":"Faraboschi, P., Brown, G., et al.: Lx: a technology platform for customizable vliw embedded processing. In: ISCA, pp. 203\u2013213 (2000)","DOI":"10.1145\/342001.339682"},{"issue":"1","key":"9_CR7","doi-asserted-by":"publisher","first-page":"66","DOI":"10.1109\/40.820055","volume":"20","author":"J. Fridman","year":"2000","unstructured":"Fridman, J., Greenfield, Z.: The tigersharc dsp architecture. IEEE Micro\u00a020(1), 66\u201376 (2000)","journal-title":"IEEE Micro"},{"key":"9_CR8","doi-asserted-by":"crossref","unstructured":"Fritts, J., Steiling, F., et al.: Mediabench ii video: expediting the next generation of video systems research. In: Proceedings of SPIE, vol.\u00a05683, p. 79 (2005)","DOI":"10.1117\/12.587955"},{"key":"9_CR9","unstructured":"Kailas, K., Ebcioglu, K., Agrawala, A.: Cars: a new code generation framework for clustered ilp processors. Technical Report UMIACS-TR-2000-55 (2000)"},{"key":"9_CR10","doi-asserted-by":"crossref","unstructured":"Kailas, K., Ebcioglu, K., Agrawala, A.: Cars: a new code generation framework for clustered ilp processors. In: HPCA, pp. 133\u2013143 (2001)","DOI":"10.1109\/HPCA.2001.903258"},{"key":"9_CR11","doi-asserted-by":"crossref","unstructured":"Lee, W., Barua, R., et al.: Space-time scheduling of instruction-level parallelism on a raw machine. In: ASPLOS (1998)","DOI":"10.1145\/291069.291018"},{"key":"9_CR12","doi-asserted-by":"publisher","first-page":"51","DOI":"10.1007\/BF01205182","volume":"7","author":"P.G. Lowney","year":"1993","unstructured":"Lowney, P.G., Freudenberger, S.M., et al.: The multiflow trace scheduling compiler. Journal of Supercomputing\u00a07, 51\u2013142 (1993)","journal-title":"Journal of Supercomputing"},{"key":"9_CR13","doi-asserted-by":"crossref","unstructured":"Muralimanohar, N., et al.: Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. In: ISPASS, pp. 100\u2013111 (2006)","DOI":"10.1109\/ISPASS.2006.1620794"},{"key":"9_CR14","doi-asserted-by":"crossref","unstructured":"Ozer, E., et al.: Unified assign and schedule: a new approach to scheduling for clustered register file microarchitectures, pp. 308\u2013315 (1998)","DOI":"10.1109\/MICRO.1998.742792"},{"key":"9_CR15","first-page":"348","volume":"1","author":"G. Pechanek","year":"2000","unstructured":"Pechanek, G., Vassiliadis, S.: The ManArray embedded processor architecture. Euromicro\u00a01, 348\u2013355 (2000)","journal-title":"Euromicro"},{"issue":"5","key":"9_CR16","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/40.877948","volume":"20","author":"H. Sharangpani","year":"2000","unstructured":"Sharangpani, H., Arora, H.: Itanium processor microarchitecture. IEEE Micro\u00a020(5), 24\u201343 (2000)","journal-title":"IEEE Micro"},{"issue":"2","key":"9_CR17","doi-asserted-by":"publisher","first-page":"11","DOI":"10.1145\/1250727.1250731","volume":"4","author":"A. Terechko","year":"2007","unstructured":"Terechko, A., Corporaal, H.: Inter-cluster communication in vliw architectures. ACM Transactions on Architecture and Code Optimization (TACO)\u00a04(2), 11 (2007)","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"}],"container-title":["Lecture Notes in Computer Science","Languages and Compilers for Parallel Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-37658-0_9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,30]],"date-time":"2025-04-30T03:19:07Z","timestamp":1745983147000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-37658-0_9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783642376573","9783642376580"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-37658-0_9","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2013]]}}}