{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T06:36:48Z","timestamp":1743057408994,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642379482"},{"type":"electronic","value":"9783642379499"}],"license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-642-37949-9_33","type":"book-chapter","created":{"date-parts":[[2013,7,4]],"date-time":"2013-07-04T07:42:10Z","timestamp":1372923730000},"page":"377-386","source":"Crossref","is-referenced-by-count":0,"title":["Design of Low Power FSM Using Verilog in VLSI"],"prefix":"10.1007","author":[{"given":"Himani","family":"Mittal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dinesh","family":"Chandra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arvind","family":"Tiwari","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"33_CR1","doi-asserted-by":"publisher","first-page":"426","DOI":"10.1109\/92.335011","volume":"2","author":"M. Alidina","year":"1994","unstructured":"Alidina, M., Monteiro, J., Devadas, S., Ghosh, A., Papaefthymiou, M.: Precomputation-based sequential logic optimization for low power. IEEE Trans. VLSI Syst.\u00a02, 426\u2013436 (1994)","journal-title":"IEEE Trans. VLSI Syst."},{"key":"33_CR2","doi-asserted-by":"crossref","unstructured":"Benini, L., De Micheli, G., Lioy, A., Macii, E., Odasso, G., Poncino, M.: Computational kernels and their application to sequential power optimization. In: Proc. 35th Design Automation Conf., pp. 764\u2013769 (June 1998)","DOI":"10.1145\/277044.277237"},{"key":"33_CR3","doi-asserted-by":"publisher","first-page":"630","DOI":"10.1109\/43.503933","volume":"15","author":"L. Benini","year":"1996","unstructured":"Benini, L., Siegel, P., De Micheli, G.: Automatic synthesis of lowpower gated-clock finite-state machines. IEEE Trans. Computer-Aided Design\u00a015, 630\u2013643 (1996)","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"33_CR4","unstructured":"Benini, L., Vuillod, P., Coelho, C., De Micheli, G.: Synthesis of lowpower partially-clocked systems from high-level specifications. Presented at the 9th Int. Symp. System Synthesis (November 1996)"},{"issue":"3","key":"33_CR5","doi-asserted-by":"publisher","first-page":"315","DOI":"10.1145\/234860.234862","volume":"1","author":"S.-H. Chow","year":"1996","unstructured":"Chow, S.-H., Ho, Y.-C., Hwang, T.: Low power realization of finite state machines\u2014A decomposition approach. ACM Trans. Design Automat. Electron. Syst.\u00a01(3), 315\u2013340 (1996)","journal-title":"ACM Trans. Design Automat. Electron. Syst."},{"key":"33_CR6","doi-asserted-by":"publisher","first-page":"1206","DOI":"10.1109\/43.41505","volume":"8","author":"S. Devadas","year":"1989","unstructured":"Devadas, S., Newton, A.: Decomposition and factorization of sequential finite state machines. IEEE Trans. Computer-Aided Design\u00a08, 1206\u20131217 (1989)","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"33_CR7","unstructured":"Hachtel, G., Hermida, M., Pardo, A., Poncino, M., Somenzi, F.: Reencoding sequential circuits to reduce power dissipation. In: Proc. Int. Conf. Computer-Aided Design, pp. 70\u201373 (November 1994)"},{"key":"33_CR8","doi-asserted-by":"crossref","unstructured":"Kernighan, B., Lin, S.: An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J., 291\u2013307 (February 1970)","DOI":"10.1002\/j.1538-7305.1970.tb01770.x"},{"key":"33_CR9","unstructured":"Monteiro, J., Devadas, S., Ghosh, A.: Retiming sequential circuits for low power. In: Proc. Int. Conf. Computer-Aided Design, pp. 398\u2013402 (November 1993)"},{"key":"33_CR10","doi-asserted-by":"crossref","unstructured":"Monteiro, J., Oliveira, A.: Finite state machine decomposition for low power. In: Proc. ACM\/IEEE Design Automation Conf., pp. 758\u2013763 (June 1998)","DOI":"10.1145\/277044.277235"}],"container-title":["Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering","Quality, Reliability, Security and Robustness in Heterogeneous Networks"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-37949-9_33","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,22]],"date-time":"2019-05-22T09:52:55Z","timestamp":1558518775000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-37949-9_33"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783642379482","9783642379499"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-37949-9_33","relation":{},"ISSN":["1867-8211","1867-822X"],"issn-type":[{"type":"print","value":"1867-8211"},{"type":"electronic","value":"1867-822X"}],"subject":[],"published":{"date-parts":[[2013]]}}}