{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T20:01:24Z","timestamp":1725739284232},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642396106"},{"type":"electronic","value":"9783642396113"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-642-39611-3_17","type":"book-chapter","created":{"date-parts":[[2013,7,3]],"date-time":"2013-07-03T18:33:07Z","timestamp":1372876387000},"page":"148-161","source":"Crossref","is-referenced-by-count":1,"title":["A Novel Approach for Implementing Microarchitectural Verification Plans in Processor Designs"],"prefix":"10.1007","author":[{"given":"Yoav","family":"Katz","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michal","family":"Rimon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Avi","family":"Ziv","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"17_CR1","unstructured":"Wile, B., Goss, J.C., Roesner, W.: Comprehensive Functional Verification - The Complete Industry Cycle. Elsevier (2005)"},{"issue":"2","key":"17_CR2","doi-asserted-by":"publisher","first-page":"84","DOI":"10.1109\/MDT.2004.1277900","volume":"21","author":"A. Adir","year":"2004","unstructured":"Adir, A., Almog, E., Fournier, L., Marcus, E., Rimon, M., Vinov, M., Ziv, A.: Genesys-Pro: Innovations in test program generation for functional processor verification. IEEE Design and Test of Computers\u00a021(2), 84\u201393 (2004)","journal-title":"IEEE Design and Test of Computers"},{"key":"17_CR3","unstructured":"Hennenhoefer, E., Typaldos, M.: The evolution of processor test generation technology, \n                  \n                    http:\/\/www.obsidiansoft.com\/pdf\/evolution.pdf"},{"issue":"3","key":"17_CR4","first-page":"13","volume":"28","author":"Y. Naveh","year":"2007","unstructured":"Naveh, Y., Rimon, M., Jaeger, I., Katz, Y., Vinov, M., Marcus, E., Shurek, G.: Constraint-based random stimuli generation for hardware verification. AI Magazine\u00a028(3), 13\u201330 (2007)","journal-title":"AI Magazine"},{"key":"17_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"146","DOI":"10.1007\/978-3-642-19583-9_15","volume-title":"Proceedings of the 6th Haifa Verification Conference","author":"J.M. Ludden","year":"2011","unstructured":"Ludden, J.M., Rimon, M., Hickerson, B.G., Adir, A.: Advances in simultaneous multithreading testcase generation methods. In: Barner, S., Kroening, D., Raz, O. (eds.) HVC 2010. LNCS, vol.\u00a06504, pp. 146\u2013160. Springer, Heidelberg (2011)"},{"key":"17_CR6","unstructured":"Burns, D.: Pre-silicon validation of hyper-threading technology. Intel Technology Journal\u00a06(1) (2002)"},{"key":"17_CR7","unstructured":"Adir, A., Bin, E., Ziv, A.: Piparazzi: A test generator for micro-architecture flow verification. In: Proceedings of the High-Level Design Validation and Test Workshop, pp. 23\u201328 (2003)"},{"key":"17_CR8","doi-asserted-by":"crossref","unstructured":"Mishra, P., Dutt, N.: Specification-driven directed test generation for validation of pipelined processors. ACM Trans. Design Autom. Electr. Syst.\u00a013(3) (2008)","DOI":"10.1145\/1367045.1367051"},{"key":"17_CR9","doi-asserted-by":"crossref","unstructured":"Fine, S., Ziv, A.: Coverage directed test generation for functional verification using Bayesian networks. In: Proceedings of the 40th Design Automation Conference, pp. 286\u2013291 (2003)","DOI":"10.1145\/775905.775907"},{"issue":"3","key":"17_CR10","doi-asserted-by":"publisher","first-page":"247","DOI":"10.1007\/s10710-005-2985-x","volume":"6","author":"G. Squillero","year":"2005","unstructured":"Squillero, G.: MicroGP\u2014an evolutionary assembly program generator. Genetic Programming and Evolvable Machines\u00a06(3), 247\u2013263 (2005)","journal-title":"Genetic Programming and Evolvable Machines"},{"issue":"6","key":"17_CR11","doi-asserted-by":"publisher","first-page":"1126","DOI":"10.1109\/TCAD.2006.884494","volume":"26","author":"I. Wagner","year":"2007","unstructured":"Wagner, I., Bertacco, V., Austin, T.: Microprocessor verification via feedback-adjusted Markov models. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a026(6), 1126\u20131138 (2007)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"17_CR12","series-title":"Lecture Notes in Artificial Intelligence","doi-asserted-by":"publisher","first-page":"154","DOI":"10.1007\/978-3-540-73847-3_20","volume-title":"Inductive Logic Programming","author":"K. Eder","year":"2007","unstructured":"Eder, K., Flach, P., Hsueh, H.-W.: Towards automating simulation-based design verification using ILP. In: Muggleton, S., Otero, R., Tamaddoni-Nezhad, A. (eds.) ILP 2006. LNCS (LNAI), vol.\u00a04455, pp. 154\u2013168. Springer, Heidelberg (2007)"},{"key":"17_CR13","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"112","DOI":"10.1007\/978-3-642-19583-9_13","volume-title":"Proceedings of the 6th Haifa Verification Conference","author":"C. Ioannides","year":"2011","unstructured":"Ioannides, C., Barrett, G., Eder, K.: Feedback-based coverage directed test generation: An industrial evaluation. In: Barner, S., Kroening, D., Raz, O. (eds.) HVC 2010. LNCS, vol.\u00a06504, pp. 112\u2013128. Springer, Heidelberg (2011)"},{"key":"17_CR14","doi-asserted-by":"crossref","unstructured":"Katz, Y., Rimon, M., Ziv, A., Shaked, G.: Learning microarchitectural behaviors to improve stimuli generation quality. In: Proceedings of the 48th Design Automation Conference, pp. 848\u2013853 (2011)","DOI":"10.1145\/2024724.2024914"},{"key":"17_CR15","doi-asserted-by":"crossref","unstructured":"Katz, Y., Rimon, M., Ziv, A.: Generating instruction streams using abstract CSP. In: Proceedings of the 2012 Design, Automation and Test in Europe Conference, pp. 15\u201320 (2012)","DOI":"10.1109\/DATE.2012.6176425"}],"container-title":["Lecture Notes in Computer Science","Hardware and Software: Verification and Testing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-39611-3_17","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,15]],"date-time":"2019-05-15T06:18:13Z","timestamp":1557901093000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-39611-3_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783642396106","9783642396113"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-39611-3_17","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2013]]}}}