{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T22:34:40Z","timestamp":1725748480094},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642408199"},{"type":"electronic","value":"9783642408205"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-642-40820-5_26","type":"book-chapter","created":{"date-parts":[[2013,9,12]],"date-time":"2013-09-12T11:19:38Z","timestamp":1378984778000},"page":"308-321","source":"Crossref","is-referenced-by-count":1,"title":["Partition-Based Hardware Transactional Memory for Many-Core Processors"],"prefix":"10.1007","author":[{"given":"Yi","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinwei","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yonghui","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Depei","family":"Qian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yali","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"26_CR1","doi-asserted-by":"crossref","unstructured":"Herlihy, M., Moss, J.E.B.: Transactional Memory Architectural Support for Lock-Free Data Structure. In: 20th International Symposium on Computer Architecture, pp. 289\u2013300. IEEE (1993)","DOI":"10.1145\/173682.165164"},{"key":"26_CR2","doi-asserted-by":"crossref","unstructured":"Moscibroda, T., Mutlu, O.: A Case for Bufferless Routing in On-Chip Networks. In: 36th International Symposium on Computer Architecture, pp. 196\u2013207. IEEE (2009)","DOI":"10.1145\/1555754.1555781"},{"key":"26_CR3","unstructured":"Hammond, L., Wong, V., Chen, M., et al.: Transactional Memory Coherence and Consistency. In: 31th International Symposium on Computer Architecture (ISCA 2004), pp. 53\u201365. IEEE CS Press (2004)"},{"key":"26_CR4","unstructured":"Scott Ananian, C., Asanovic, K., Kuszmaul, B.C., et al.: Unbounded Transactional Memory. In: 11th International Symposium on High-Performance Computer Architecture (HPCA 2005), pp. 316\u2013327. IEEE CS Press (2005)"},{"key":"26_CR5","unstructured":"Moore Kevin, E., Jayaram, B., Moravan Michelle, J., et al.: LogTM: log-based transactional memory. In: 12th International Symposium on High-Performance Computer Architecture (HPCA 2006), pp. 258\u2013269. IEEE CS Press (2006)"},{"key":"26_CR6","doi-asserted-by":"crossref","unstructured":"Ceze, L., Tuck, J., et al.: Bulk Disambiguation of Speculative Threads in Multiprocessors. In: 33rd International Symposium on Computer Architecture, pp. 227\u2013238 (2006)","DOI":"10.1145\/1150019.1136506"},{"key":"26_CR7","doi-asserted-by":"crossref","unstructured":"Shriraman, A., Spear, M.F., et al.: An Integrated Hardware-Software Approach to Flexible Transactional Memory. In: 34th Annual International Symposium on Computer Architecture, pp. 104\u2013115. ACM (2007)","DOI":"10.1145\/1250662.1250676"},{"key":"26_CR8","doi-asserted-by":"crossref","unstructured":"Shriraman, A., Dwarkadas, S., Scott, M.L.: Flexible Decoupled Transactional Memory Support. In: 35th International Symposium on Computer Architecture, pp. 139\u2013150. IEEE & ACM (2008)","DOI":"10.1145\/1394608.1382134"},{"key":"26_CR9","doi-asserted-by":"crossref","unstructured":"Kumar, S., Chu, M., Hughes, C.J., et al.: Hybrid Transactional Memory. In: 11th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 209\u2013220. ACM Press (2006)","DOI":"10.1145\/1122971.1123003"},{"key":"26_CR10","doi-asserted-by":"crossref","unstructured":"Rajwar, R., Herlihy, M., Lai, K.: Virtualizing Transactional Memory. In: 32nd International Symposium on Computer Architecture, pp. 495\u2013505. IEEE CS Press (2005)","DOI":"10.1145\/1080695.1070011"},{"key":"26_CR11","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"138","DOI":"10.1007\/978-3-642-11950-7_13","volume-title":"Architecture of Computing Systems - ARCS 2010","author":"Y. Liu","year":"2010","unstructured":"Liu, Y., Su, Y., Zhang, C., Wu, M., Zhang, X., Li, H., Qian, D.: Efficient Transaction Nesting in Hardware Transactional Memory. In: M\u00fcller-Schloer, C., Karl, W., Yehia, S. (eds.) ARCS 2010. LNCS, vol.\u00a05974, pp. 138\u2013149. Springer, Heidelberg (2010)"},{"key":"26_CR12","unstructured":"Taylor, M.B., Lee, W., Miller, J., et al.: Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ILP and streams. In: 31st Annual International Symposium on Computer Architecture, pp. 2\u201313 (2004)"},{"key":"26_CR13","doi-asserted-by":"crossref","unstructured":"Martin, M.M.K., Sorin, D.J., Beckmann, B.M., et al.: Multifacet\u2019s General Execution-driven Multiprocessor Simulator (GEMS) Toolset. SIGARCH Computer Architecture News, 92\u201399 (November 2005)","DOI":"10.1145\/1105734.1105747"},{"issue":"2","key":"26_CR14","doi-asserted-by":"publisher","first-page":"50","DOI":"10.1109\/2.982916","volume":"35","author":"P.S. Magnusson","year":"2002","unstructured":"Magnusson, P.S., Christensson, M., Eskilson, J., et al.: Simics: A full system simulation platform. IEEE Computer Society\u00a035(2), 50\u201358 (2002)","journal-title":"IEEE Computer Society"},{"key":"26_CR15","unstructured":"Minh, C.C., Chung, J., Kozyrakis, C., et al.: STAMP: Stanford Transactional Applications for Multi-Processing. In: 2008 IEEE International Symposium on Workload Characterization, pp. 35\u201346. IEEE CS Press (2008)"},{"key":"26_CR16","doi-asserted-by":"crossref","unstructured":"Bloom, B.H.: Space\/time trade-offs in hash coding with allowable errors. Communications of the ACM, 422\u2013426 (1970)","DOI":"10.1145\/362686.362692"},{"key":"26_CR17","doi-asserted-by":"crossref","unstructured":"Gramoli, V., Guerraoui, R., Trigonakis, V.: TM2C: a Software Transactional Memory for Many-Cores. In: ACM European Conference on Computer Systems (EuroSys 2012), pp. 351\u2013364 (2012)","DOI":"10.1145\/2168836.2168872"}],"container-title":["Lecture Notes in Computer Science","Network and Parallel Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-40820-5_26","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,17]],"date-time":"2019-05-17T06:08:56Z","timestamp":1558073336000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-40820-5_26"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783642408199","9783642408205"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-40820-5_26","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2013]]}}}