{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,2]],"date-time":"2025-05-02T04:03:21Z","timestamp":1746158601156,"version":"3.40.4"},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642420238"},{"type":"electronic","value":"9783642420245"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-642-42024-5_11","type":"book-chapter","created":{"date-parts":[[2013,12,13]],"date-time":"2013-12-13T14:41:21Z","timestamp":1386945681000},"page":"83-93","source":"Crossref","is-referenced-by-count":0,"title":["Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence"],"prefix":"10.1007","author":[{"given":"Sumanta","family":"Pyne","sequence":"first","affiliation":[]},{"given":"Ajit","family":"Pal","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"11_CR1","doi-asserted-by":"crossref","unstructured":"Caignet, F., Delmas-Bendhia, S., Sicard, E.: The Challenge of Signal Integrity in Deep-submicrometer CMOS Technology. Proceedings of the IEEE\u00a089(4), 556\u2013573","DOI":"10.1109\/5.920583"},{"key":"11_CR2","doi-asserted-by":"crossref","unstructured":"Sylvester, D., Hu, C.: Analytical Modeling and Characterization of Deepsubmicrometer Interconnect. Proceedings of the IEEE\u00a089(5), 634\u2013664","DOI":"10.1109\/5.929648"},{"key":"11_CR3","doi-asserted-by":"crossref","unstructured":"Victor, B., Keutzer, K.: Bus Encoding to Prevent Crosstalk Delay. In: Proceedings of ICCAD, pp. 57\u201363 (2001)","DOI":"10.1109\/ICCAD.2001.968598"},{"key":"11_CR4","unstructured":"Tiwari, V., Malik, S., Wolfe, A.: Compilation Techniques for Low Energy: An Overview. In: Proceedings of Symposium on Low-Power Electronics, San Diego, CA (October 1994)"},{"key":"11_CR5","unstructured":"Su, C.-L., Tsui, C.-Y., Despain, A.M.: Reducing Power Consumption at Control Path of High Performance Microprocessors. IEEE Design and Test of Computers (December 1994)"},{"key":"11_CR6","unstructured":"Lee, C., Lee, J.K., Hwang, T.T.: Compiler Optimization on Instruction Scheduling for Low Power. In: Proceedings of 13th International Symposium on System Synthesis, pp. 55\u201360 (2000)"},{"key":"11_CR7","doi-asserted-by":"crossref","unstructured":"Lee, C., Lee, J.K., Hwang, T.T., Tsai, S.: Compiler Optimization on VLIW Instruction Scheduling for Low Power. ACM Transactions on Design Automation of Electronic Systems (TODAES)\u00a08(2), 252\u2013268","DOI":"10.1145\/762488.762494"},{"key":"11_CR8","doi-asserted-by":"crossref","unstructured":"Parikh, A., Kim, S., Kandemir, M., Vijaykrishnan, N., Irwin, M.J.: Instruction Scheduling for Low Power. Journal of VLSI Signal Processing 37(1), 129\u2013149","DOI":"10.1023\/B:VLSI.0000017007.28247.f6"},{"key":"11_CR9","doi-asserted-by":"crossref","unstructured":"Shao, Z., Xiao, B., Xue, C., Zhuge, Q., Sha, E.H.M.: Loop scheduling with timing and switching-activity minimization for VLIW DSP. ACM Transactions on Design Automation of Electronic Systems (TODAES)\u00a011(1), 165\u2013185","DOI":"10.1145\/1124713.1124724"},{"key":"11_CR10","unstructured":"Shin, D., Kim, J., Chang, N.: An Operation Rearrangement Technique for Low-Power VLIW Instruction Fetch. In: Proceedings of DATE, p. 809 (2001)"},{"key":"11_CR11","doi-asserted-by":"crossref","unstructured":"Shao, Z., Xiao, B., Xue, C., Sha, E.H.M.: Algorithms and analysis of scheduling for loops with minimum switching. Int. J. Computational Science and Engineering\u00a02(1\/2)","DOI":"10.1504\/IJCSE.2006.009939"},{"key":"11_CR12","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"300","DOI":"10.1007\/978-3-540-74442-9_29","volume-title":"Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation","author":"Z. Herczeg","year":"2007","unstructured":"Herczeg, Z., Kiss, \u00c1., Schmidt, D., Wehn, N., Gyim\u00f3thy, T.: XEEMU: An Improved XScale Power Simulator. In: Az\u00e9mard, N., Svensson, L. (eds.) PATMOS 2007. LNCS, vol.\u00a04644, pp. 300\u2013309. Springer, Heidelberg (2007)"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-42024-5_11","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T05:04:59Z","timestamp":1746075899000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-42024-5_11"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783642420238","9783642420245"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-42024-5_11","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2013]]}}}