{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:33:08Z","timestamp":1758893588611,"version":"3.40.4"},"publisher-location":"Berlin, Heidelberg","reference-count":6,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642420238"},{"type":"electronic","value":"9783642420245"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-642-42024-5_14","type":"book-chapter","created":{"date-parts":[[2013,12,13]],"date-time":"2013-12-13T14:41:21Z","timestamp":1386945681000},"page":"108-117","source":"Crossref","is-referenced-by-count":4,"title":["Characterization of Logical Effort for Improved Delay"],"prefix":"10.1007","author":[{"given":"Sachin","family":"Maheshwari","sequence":"first","affiliation":[]},{"given":"Himadri Singh","family":"Raghav","sequence":"additional","affiliation":[]},{"given":"Anu","family":"Gupta","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"14_CR1","unstructured":"Sutherland, D.H.I., Sproull, B.: Logical Effort: designing fast CMOS circuits. Morgan Kaufmann (1999)"},{"key":"14_CR2","doi-asserted-by":"crossref","unstructured":"Lasbouygues, B., Engels, S., Wilson, R., Maurine, P., Az\u00e9mard, N., Auvergne, D.: Logical Effort Model Extension to Propagation Delay Representation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a025(9) (September 2006)","DOI":"10.1109\/TCAD.2005.857400"},{"issue":"6","key":"14_CR3","doi-asserted-by":"publisher","first-page":"937","DOI":"10.1109\/TCAD.2005.847892","volume":"24","author":"A. Kabbani","year":"2005","unstructured":"Kabbani, A., Al-Khalili, D., Al-Khalili, A.J.: Delay analysis of CMOS gates using modified logical effort model. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.\u00a024(6), 937\u2013947 (2005)","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"14_CR4","doi-asserted-by":"crossref","unstructured":"Dao, H., Oklobdzija, V.G.: Application of Logical Effort Techniques for Speed Optimization and Analysis of Representative Adders. In: 35th Asilomar Conference on Signals, Systems and Computers, California, vol.\u00a02, pp. 1666\u20131669 (2001)","DOI":"10.1109\/ACSSC.2001.987768"},{"key":"14_CR5","unstructured":"Raghav, H.S., Maheshwari, S., Gupta, A.: A Comparative Analysis of Power & Delay Optimize Digital Logic Families for High Performance System Design. In: International Conference on Electronic Systems, NIT Rourkela, India, pp. 174\u2013177 (2011)"},{"key":"14_CR6","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"J.M. Rabaey","year":"2003","unstructured":"Rabaey, J.M., Chandrakasan, A., Nikoli\u0107, B.: Digital Integrated Circuits: A Design Perspective, 2nd edn. Prentice-Hall, New Jersey (2003)","edition":"2"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-42024-5_14","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T05:04:09Z","timestamp":1746075849000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-42024-5_14"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783642420238","9783642420245"],"references-count":6,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-42024-5_14","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2013]]}}}