{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:42:18Z","timestamp":1761648138690,"version":"3.40.4"},"publisher-location":"Berlin, Heidelberg","reference-count":13,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642420238"},{"type":"electronic","value":"9783642420245"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-642-42024-5_18","type":"book-chapter","created":{"date-parts":[[2013,12,13]],"date-time":"2013-12-13T14:41:21Z","timestamp":1386945681000},"page":"146-152","source":"Crossref","is-referenced-by-count":3,"title":["A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits"],"prefix":"10.1007","author":[{"given":"Surabhi","family":"Singh","sequence":"first","affiliation":[]},{"given":"Brajesh K.","family":"Kaushik","sequence":"additional","affiliation":[]},{"given":"Sudeb","family":"Dasgupta","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"18_CR1","doi-asserted-by":"crossref","unstructured":"Singh, S., Kaur, B., Kaushik, B.K., Dasgupta, S.: Leakage Current Reduction using Modified Gate Replacement Technique for CMOS VLSI Circuit. In: Proc. IEEE CODIS 2012, Kolkata, pp. 464\u2013467 (2012)","DOI":"10.1109\/CODIS.2012.6422239"},{"key":"18_CR2","doi-asserted-by":"publisher","first-page":"305","DOI":"10.1109\/JPROC.2002.808156","volume":"91","author":"K. Roy","year":"2003","unstructured":"Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-sub micrometer CMOS circuits. Proc. of IEEE\u00a091, 305\u2013327 (2003)","journal-title":"Proc. of IEEE"},{"key":"18_CR3","doi-asserted-by":"crossref","unstructured":"Mukhopadhyay, S., Roy, K.: Accurate Modeling of Transistor Stacks to Effectively Reduce Total Standby Leakage in Nano-Scale CMOS Circuits. In: IEEE Int. Symp. VLSI Circuit Digest, pp. 53\u201356 (2003)","DOI":"10.1109\/VLSIC.2003.1221159"},{"key":"18_CR4","doi-asserted-by":"publisher","first-page":"140","DOI":"10.1109\/TVLSI.2003.821546","volume":"12","author":"A. Abdollahi","year":"2004","unstructured":"Abdollahi, A., Fallah, F., Pedram, M.: Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Trans. Very Large Scale Integration Systems (VLSI)\u00a012, 140\u2013154 (2004)","journal-title":"IEEE Trans. Very Large Scale Integration Systems (VLSI)"},{"key":"18_CR5","doi-asserted-by":"publisher","first-page":"173","DOI":"10.1109\/TVLSI.2005.863747","volume":"14","author":"L. Yuan","year":"2006","unstructured":"Yuan, L., Qu, G.: A Combined Gate Replacement and Input Vector Control Approach for Leakage Current Reduction. IEEE Trans. Very Large Integration (VLSI) Systems\u00a014, 173\u2013182 (2006)","journal-title":"IEEE Trans. Very Large Integration (VLSI) Systems"},{"key":"18_CR6","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1870109.1870118","volume":"16","author":"N. Jayakumar","year":"2010","unstructured":"Jayakumar, N., Khatri, S.P.: A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty. ACM Transactions on Design Automation of Electronic Systems (TODAES)\u00a016, 9:1\u20139:20 (2010)","journal-title":"ACM Transactions on Design Automation of Electronic Systems (TODAES)"},{"key":"18_CR7","doi-asserted-by":"publisher","first-page":"1362","DOI":"10.1109\/TVLSI.2005.862723","volume":"13","author":"A.K. Sultania","year":"2005","unstructured":"Sultania, A.K., Sylvester, D., Sapatnekar, S.S.: Gate oxide leakage and delay tradeoffs for Dual-T ox circuits. IEEE Trans. Very Large Integration (VLSI) Systems\u00a013, 1362\u20131375 (2005)","journal-title":"IEEE Trans. Very Large Integration (VLSI) Systems"},{"key":"18_CR8","volume-title":"Digital integrated circuits","author":"J.M. Rabaey","year":"2002","unstructured":"Rabaey, J.M., Chandrakasan, A., Nikolic, B.: Digital integrated circuits. Prentic Hall, New Jersey (2002)"},{"key":"18_CR9","unstructured":"Kang, S.-M., Leblebici, Y.: CMOS Digital Integrated Circuits: Analysis and Design, 3rd edn. Tata McGraw-Hill Publishers (2002)"},{"key":"18_CR10","first-page":"2561","volume":"25","author":"F. Gao","year":"2006","unstructured":"Gao, F., Hayes, J.P.: Exact and heuristic approaches to input vector control for leakage power reduction. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems\u00a025, 2561\u20132574 (2006)","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"18_CR11","doi-asserted-by":"crossref","unstructured":"Chen, Z., Johnson, M., Wei, L., Roy, K.: Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. In: IEEE Int. Symp. Low Power Electronics and Design (ISLPED 1998), pp. 239\u2013244 (1998)","DOI":"10.1145\/280756.280917"},{"key":"18_CR12","unstructured":"http:\/\/www.cad.polito.it\/downloads\/tools\/benchmarks.html"},{"key":"18_CR13","unstructured":"http:\/\/www.ece.uic.edu\/~masud\/resources.html"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-42024-5_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T05:03:30Z","timestamp":1746075810000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-42024-5_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783642420238","9783642420245"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-42024-5_18","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2013]]}}}