{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T16:11:11Z","timestamp":1746115871164,"version":"3.40.4"},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642452925"},{"type":"electronic","value":"9783642452932"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-642-45293-2_23","type":"book-chapter","created":{"date-parts":[[2013,11,25]],"date-time":"2013-11-25T13:47:06Z","timestamp":1385387226000},"page":"307-318","source":"Crossref","is-referenced-by-count":0,"title":["An Improved FPGAs-Based Loop Pipeline Scheduling Algorithm for Reconfigurable Compiler"],"prefix":"10.1007","author":[{"given":"Zhenhua","family":"Guo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yanxia","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guoyin","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tianxiang","family":"Sui","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"23_CR1","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1749603.1749604","volume":"42","author":"J.M.P. Cardoso","year":"2010","unstructured":"Cardoso, J.M.P., Diniz, P.C., Weinhardt, M.: Compiling for Reconfigurable Computing: A Survey. ACM Computing Surveys\u00a042, 1\u201365 (2010)","journal-title":"ACM Computing Surveys"},{"key":"23_CR2","doi-asserted-by":"crossref","unstructured":"Gokhale, M.B., Stone, J.M.: NAPA C: compiling for a hybrid RISC\/FPGA architecture. In: Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), Napa Valley, California, pp. 126\u2013135 (1998)","DOI":"10.1109\/FPGA.1998.707890"},{"key":"23_CR3","doi-asserted-by":"crossref","unstructured":"Callahan, T.: Kernel Formation in Garpcc. In: Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, vol. 04, pp. 308\u2013309 (2003)","DOI":"10.1109\/FPGA.2003.1227283"},{"key":"23_CR4","doi-asserted-by":"crossref","unstructured":"Stockwood, J., Harr, R., Callahan, T., et al.: Hardware-Software Co-Design of Embedded Reconfigurable Architectures. In: 37th Conference on Design Automation (DAC 2000), pp. 507\u2013512 (2000)","DOI":"10.1145\/337292.337559"},{"key":"23_CR5","doi-asserted-by":"crossref","unstructured":"Alex, D., Jones, B., et al.: PACT HDL: A C Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations. In: Proc. of the 2002 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 188\u2013197 (2002)","DOI":"10.1145\/581630.581659"},{"key":"23_CR6","unstructured":"Shen, Y.: Research on the hardware-software code partition technology of reconfigurable computing systems. University of Science and Technology of China, pp. 35\u201339 (2007)"},{"key":"23_CR7","doi-asserted-by":"crossref","unstructured":"Qu, J., Zhao, R., Liu, T., et al.: The Research of FPGA-based Loop Optimization Pipeline Scheduling Technology. In: Computer and Communication Technologies in Agriculture Engineering International Conference on IEEE (CCTAE 2010), vol.\u00a03, pp. 426\u2013429 (2010)","DOI":"10.1109\/CCTAE.2010.5544187"},{"issue":"3","key":"23_CR8","first-page":"267","volume":"5","author":"Y. Wu","year":"2011","unstructured":"Wu, Y., Gu, G., et al.: Application-Specific Compiler for Reconfigurable Architecture ASCRA. Jisuanji Kexue yu Tansuo\u00a05(3), 267\u2013279 (2011)","journal-title":"Jisuanji Kexue yu Tansuo"},{"key":"23_CR9","doi-asserted-by":"crossref","unstructured":"Lattner, C., Adve, V.: LLVM: A compilation framework for lifelong program analysis & transformation. In: International Symposium on Code Generation and Optimization (CGO), pp. 75\u201386. IEEE (2004)","DOI":"10.1109\/CGO.2004.1281665"},{"key":"23_CR10","volume-title":"Practical FPGA programming in C","author":"D. Pellerin","year":"2005","unstructured":"Pellerin, D., Thibault, S.: Practical FPGA programming in C. Prentice Hall Press, Upper Saddle River (2005)"},{"key":"23_CR11","unstructured":"http:\/\/www.xilinx.com\/products\/design-tools\/vivado\/index.htm"},{"key":"23_CR12","doi-asserted-by":"crossref","unstructured":"Guo, Z., Najjar, W.: A compiler intermediate representation for reconfigurable fabrics. In: Proceedings of the Conf. on Field Programmable Logic and Applications (FPL 2006), pp. 1\u20134 (2006)","DOI":"10.1109\/FPL.2006.311304"}],"container-title":["Lecture Notes in Computer Science","Advanced Parallel Processing Technologies"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-45293-2_23","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,30]],"date-time":"2025-04-30T23:03:35Z","timestamp":1746054215000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-45293-2_23"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783642452925","9783642452932"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-45293-2_23","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2013]]}}}