{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T23:41:50Z","timestamp":1725666110512},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540182948"},{"type":"electronic","value":"9783642456282"}],"license":[{"start":{"date-parts":[[1987,1,1]],"date-time":"1987-01-01T00:00:00Z","timestamp":536457600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1987]]},"DOI":"10.1007\/978-3-642-45628-2_8","type":"book-chapter","created":{"date-parts":[[2012,3,5]],"date-time":"2012-03-05T16:25:11Z","timestamp":1330964711000},"page":"83-94","source":"Crossref","is-referenced-by-count":2,"title":["Fault Detection by Consumption Measurement in CMOS Circuits"],"prefix":"10.1007","author":[{"given":"Mireille","family":"Jacomino","sequence":"first","affiliation":[]},{"given":"Jean Luc","family":"Rainard","sequence":"additional","affiliation":[]},{"given":"Ren\u00e9","family":"David","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"8_CR1","doi-asserted-by":"crossref","unstructured":"R. H. Wadsack, \u201cFault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits,\u201d the Bell Systems Technical Journal, vol 57, no 5, May 1978.","DOI":"10.1002\/j.1538-7305.1978.tb02106.x"},{"key":"8_CR2","unstructured":"D. Baschiera B. Courtois, \u201cTesting CMOS: a Challenge,\u201d Proceeding of VLSI Design, pp. 58-62, October 84."},{"key":"8_CR3","unstructured":"D. Baschiera B. Courtois, \u201cTesting for S-open, S-on and Shorts,\u201d Rapport de recherche au laboratoire TIM3\/IMAG, Mai 85."},{"key":"8_CR4","unstructured":"S. M. Reddy M. K. Reddy J. G. Kuhl, \u201cOn Testable Design for CMOS Logic Circuits,\u201d Proceeding of International Test Conference 1983, paper 15.2, pp. 35-445."},{"key":"8_CR5","unstructured":"J. A. Brzozowski, \u201cTestability of CMOS Cells,\u201d Proceeding of VAIL, April 86."},{"key":"8_CR6","doi-asserted-by":"crossref","unstructured":"J. M. Acken, \u201cTesting for Bridging Faults [Shorts] in CMOS Circuits,\u201d Proceeding of 20th Design Automation Conference 1983 IEEE, paper 45.4, pp. 717-718.","DOI":"10.1109\/DAC.1983.1585734"},{"key":"8_CR7","unstructured":"K. Wagner, \u201cDelay Testing of Digital Circuits Using Pseudorandom Input Sequences,\u201d CRC Report No 86, May 1986."},{"key":"8_CR8","unstructured":"Dr J. J. Shedletsky, \u201cDelay Testing LSI Logic,\u201d IBM T.J. Watson Research Center Yorktown Heights, pp. 159-164."},{"key":"8_CR9","unstructured":"M. W. Levi, \u201cCMOS is Most Testable,\u201d Proceeding of International Test Conference 1981 IEEE, paper 9.3, pp. 217-220."}],"container-title":["Informatik-Fachberichte","Fehlertolerierende Rechensysteme \/ Fault-Tolerant Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-45628-2_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,15]],"date-time":"2019-05-15T05:17:13Z","timestamp":1557897433000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-45628-2_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1987]]},"ISBN":["9783540182948","9783642456282"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-45628-2_8","relation":{},"ISSN":["0343-3005"],"issn-type":[{"type":"print","value":"0343-3005"}],"subject":[],"published":{"date-parts":[[1987]]}}}