{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T05:05:24Z","timestamp":1725599124665},"publisher-location":"Berlin, Heidelberg","reference-count":37,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540678809"},{"type":"electronic","value":"9783642583223"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/978-3-642-58322-3_17","type":"book-chapter","created":{"date-parts":[[2011,8,4]],"date-time":"2011-08-04T23:05:05Z","timestamp":1312499105000},"page":"197-215","source":"Crossref","is-referenced-by-count":0,"title":["PROPAN: Ein retargierbares System f\u00fcr Postpassoptimierungen und -analysen"],"prefix":"10.1007","author":[{"given":"Daniel","family":"K\u00e4stner","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"unstructured":"Analog Devices. ADSP-2106x SHARC User\u2019s Manual, 1995.","key":"17_CR1"},{"key":"17_CR2","volume-title":"IEEE Transactions on Computers","author":"S Arya","year":"1985","unstructured":"S. Arya. An Optimal Instruction Scheduling Model for a Class of Vector Processors. IEEE Transactions on Computers, 1985."},{"key":"17_CR3","first-page":"1","volume-title":"Design Automation for Embedded Systems","author":"S Bashford","year":"1999","unstructured":"S. Bashford and R. Leupers. Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths. Design Automation for Embedded Systems, pages 1\u201350, 1999."},{"key":"17_CR4","volume-title":"INRIA","author":"F Bodin","year":"1997","unstructured":"F. Bodin, Z. Chamski, E. Rohou, and A. Seznec. Functional Specification of SALTO: A Retargetable System for Assembly Language Transformation and Optimization, rev. 1.00 beta. INRIA, 1997."},{"key":"17_CR5","volume-title":"Siemens AG","author":"E Farquhar","year":"1997","unstructured":"E. Farquhar and E. Hadad. TriCore Architecture Manual. Siemens AG, 1997."},{"key":"17_CR6","first-page":"503","volume-title":"Proceedings of the EDAC","author":"A Faut h","year":"1995","unstructured":"A. Faut h, J. Van Praet, and M. Freericks. Describing Instruction Set Processors Using nML. In Proceedings of the EDAC, pages 503\u2013507. IEEE, 1995."},{"key":"17_CR7","volume-title":"PhD thesis","author":"C Ferdinand","year":"1997","unstructured":"C. Ferdinand. Cache Behavior Prediction for Real-Time Systems. PhD thesis, Saarland University, 1997."},{"key":"17_CR8","volume-title":"Run-Time Guarantees for Real-Time Systems \u2014 The USES Approach","author":"C Ferdinand","year":"1999","unstructured":"C. Ferdinand, D. K\u00e4stner, M. Langenbach, F. Martin, M. Schmidt, J. Schneider, J. Theiling, S. Thesing, and R. Wilhelm. Run-Time Guarantees for Real-Time Systems \u2014 The USES Approach. Proceedings of the ATPS, 1999."},{"key":"17_CR9","first-page":"478","volume-title":"IEEE Transactions on Computers","author":"JA Fisher","year":"1981","unstructured":"J.A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transactions on Computers, pages 478\u2013490, 1981."},{"key":"17_CR10","first-page":"1266","volume-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","author":"CH Gebotys","year":"1993","unstructured":"C.H. Gebotys and M.I. Elmasry. Global Optimization Approach for Architectural Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1266\u20131278, 1993."},{"doi-asserted-by":"crossref","unstructured":"R. Govindarajan, Erik R. Altman, and Guang R. Gao. A Framework for Resource Constrained Rate Optimal Software Pipelining. IEEE Transactions on Parallel and Distributed Systems, (11), 1996.","key":"17_CR11","DOI":"10.1109\/71.544355"},{"key":"17_CR12","series-title":"Technical report","volume-title":"ISDL: Instruction Set Description Language Version 1.0","author":"G Hadjiyiannis","year":"1998","unstructured":"G. Hadjiyiannis. ISDL: Instruction Set Description Language Version 1.0. Technical report, MIT RLE, 1998."},{"key":"17_CR13","volume-title":"DATE","author":"A Halambi","year":"1999","unstructured":"A. Halambi, P. Grun, V. Ganesh, Khare A., N. Dutt, and A. Nicolau. EXPRESSION: A Language for Architecture Exploration through Compiler\/Simulator Re-targetability. DATE, 1999."},{"key":"17_CR14","volume-title":"Proceedings of the D AC","author":"S Hanono","year":"1998","unstructured":"S. Hanono and S. Devadas. Instruction Scheduling, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Proceedings of the D AC. ACM, 1998."},{"unstructured":"ILOG S.A. ILOG CPLEX 6.5 User\u2019s Manual, 1999.","key":"17_CR15"},{"key":"17_CR16","volume-title":"PhD thesis","author":"D K\u00e4stner","year":"2000","unstructured":"D. K\u00e4stner. Retargetable Code Optimization by Integer Linear Programming. PhD thesis, Saarland University, 2000. To appear."},{"key":"17_CR17","series-title":"Technical report, Transferbereich","volume-title":"TDL: A Hardware and Assembly Description Language","author":"D K\u00e4stner","year":"2000","unstructured":"D. K\u00e4stner. TDL: A Hardware and Assembly Description Language. Technical report, Transferbereich 14, Saarland University, 2000."},{"key":"17_CR18","series-title":"Technical report","volume-title":"Integer Linear Programming vs. Graph-Based Methods in Code Generation","author":"D K\u00e4stner","year":"1998","unstructured":"D. K\u00e4stner and M. Langenbach. Integer Linear Programming vs. Graph-Based Methods in Code Generation. Technical report, Saarland University, 1998."},{"key":"17_CR19","first-page":"122","volume-title":"Proceedings of the CC","author":"D K\u00e4stner","year":"1999","unstructured":"D. K\u00e4stner and M. Langenbach. Code Optimization by Integer Linear Programming. In Proceedings of the CC, pages 122\u2013136, 1999."},{"key":"17_CR20","volume-title":"Proceedings of the LCTES Workshop","author":"D K\u00e4stner","year":"1998","unstructured":"D. K\u00e4stner and S. Thesing. Cache Sensitive Pre-Runtime Scheduling. In Proceedings of the LCTES Workshop, 1998."},{"key":"17_CR21","volume-title":"Master\u2019s thesis","author":"D K\u00e4stner","year":"1997","unstructured":"Daniel K\u00e4stner. Instruktionsanordnung und Registerallokation auf der Basis ganzzahliger linearer Programmierung f\u00fcr den digitalen Signalprozessor ADSP-2106x. Master\u2019s thesis, Saarland University, 1997."},{"key":"17_CR22","volume-title":"Mathematical Communications","author":"D K\u00e4stner","year":"1999","unstructured":"K\u00e4stner, D. and Wilhelm, R. Operations research methods in compiler backends. Mathematical Communications, 1999."},{"key":"17_CR23","series-title":"Technical report","volume-title":"CRL \u2014 Uniform Representation for Control Flow","author":"M Langenbach","year":"1998","unstructured":"M. Langenbach. CRL \u2014 A Uniform Representation for Control Flow. Technical report, Transferbereich 14, Saarland University, November 1998."},{"key":"17_CR24","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2570-4","volume-title":"Retargetable Code Generation for Digital Signal Processors","author":"R Leupers","year":"1997","unstructured":"R. Leupers. Retargetable Code Generation for Digital Signal Processors. Kluwer Academic Publishers, 1997."},{"key":"17_CR25","volume-title":"VHDL: Hardware Description and Design","author":"R Lipsett","year":"1993","unstructured":"R. Lipsett, C. Schaefer, and C. Ussery. VHDL: Hardware Description and Design. Kluwer Academic Publishers, 12. edition, 1993.","edition":"12"},{"key":"17_CR26","volume-title":"Code Generation for Embedded Processors","author":"P Marwedel","year":"1995","unstructured":"P. Marwedel and G. Goossens. Code Generation for Embedded Processors. Kluwer, 1995."},{"key":"17_CR27","first-page":"16","volume-title":"Languages and Compilers for Parallel Computing","author":"S Novack","year":"1994","unstructured":"S. Novack and A. Nicolau. Mutation scheduling: A Unified Approach to Compiling for fine-grain Parallelism. In Languages and Compilers for Parallel Computing, pages 16\u201330. Springer LNCS, 1994."},{"key":"17_CR28","doi-asserted-by":"publisher","first-page":"126","DOI":"10.1145\/255305.255329","volume-title":"20th Annual Workshop on Microprogramming","author":"L Nowak","year":"1987","unstructured":"L. Nowak. Graph Based Retargetable Microcode Compilation in the MIM\u00d3LA Design System. 20th Annual Workshop on Microprogramming, pages 126\u2013132, 1987."},{"key":"17_CR29","volume-title":"TriMedia TM1000 Preliminary Data Book","author":"Philips Electronics North America Corporation","year":"1997","unstructured":"Philips Electronics North America Corporation. TriMedia TM1000 Preliminary Data Book, 1997."},{"key":"17_CR30","first-page":"1","volume-title":"Proceedings of the PLDI","author":"J Ruttenberg","year":"1996","unstructured":"J. Ruttenberg, G.R. Gao, A. Stoutchinin, and W. Lichtenstein. Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler. Proceedings of the PLDI, pages 1\u201311, 1996."},{"key":"17_CR31","volume-title":"Proceedings of the ASPLOS","author":"MAR Saghir","year":"1996","unstructured":"M.A.R. Saghir, P. Chow, and C.G. Lee. Exploiting Dual Data-Memory Banks in Digital Signal Processors. Proceedings of the ASPLOS, 1996."},{"key":"17_CR32","volume-title":"PhD thesis","author":"A Sudarsanam","year":"1998","unstructured":"A. Sudarsanam. Code Optimization Libraries For Retargetable Compilation For Embedded Digital Signal Processors. PhD thesis, University of Princeton, 1998."},{"unstructured":"Texas Instruments. TMS320C62xx Programmer\u2019s Guide, 1997.","key":"17_CR33"},{"key":"17_CR34","volume-title":"Compiler Design","author":"R Wilhelm","year":"1995","unstructured":"R. Wilhelm and D. Maurer. Compiler Design. Addison-Wesley, 1995."},{"key":"17_CR35","volume-title":"Model Building in Mathematical Programming","author":"HP Williams","year":"1993","unstructured":"H.P. Williams. Model Building in Mathematical Programming. John Wiley and Sons, New York, 3. edition, 1993.","edition":"3"},{"key":"17_CR36","volume-title":"PhD thesis","author":"L Zhang","year":"1996","unstructured":"L. Zhang. SILP. Scheduling and Allocating with Integer Linear Programming. PhD thesis, Saarland University, 1996."},{"key":"17_CR37","volume-title":"Proceedings of the International Conference on Integrated Systems for Signal Processing","author":"V Zivojnovic","year":"1994","unstructured":"V. Zivojnovic, J. M. Velarde, C. Schl\u00e4ger, and H. Meyr. DSPSTONE: A DSP-Oriented Benchmarking Methodology. In Proceedings of the International Conference on Integrated Systems for Signal Processing, 1994."}],"container-title":["Informatik aktuell","Informatik 2000"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-58322-3_17","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,13]],"date-time":"2019-06-13T16:06:32Z","timestamp":1560441992000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-58322-3_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540678809","9783642583223"],"references-count":37,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-58322-3_17","relation":{},"ISSN":["1431-472X"],"issn-type":[{"type":"print","value":"1431-472X"}],"subject":[],"published":{"date-parts":[[2000]]}}}