{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T12:10:46Z","timestamp":1725624646358},"publisher-location":"Berlin, Heidelberg","reference-count":33,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540103899"},{"type":"electronic","value":"9783642678394"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1980]]},"DOI":"10.1007\/978-3-642-67839-4_8","type":"book-chapter","created":{"date-parts":[[2011,10,25]],"date-time":"2011-10-25T08:51:27Z","timestamp":1319532687000},"page":"92-103","source":"Crossref","is-referenced-by-count":0,"title":["Rechnergest\u00fctzter Entwurf Integrierter Schaltungen"],"prefix":"10.1007","author":[{"given":"O.","family":"Manck","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"8_CR1","volume-title":"Finite Difference Methods for partial differential equations","author":"GE Forsythe","year":"1960","unstructured":"G. E. Forsythe, W. R. Wasow, \u201eFinite Difference Methods for partial differential equations\u201c, Wiley, New York, 1960"},{"key":"8_CR2","volume-title":"Matrix Iterative Analysis","author":"RS Varga","year":"1962","unstructured":"R. S. Varga, \u201eMatrix Iterative Analysis\u201c, Prentice-Hall, Englewood Clifts, N. J., 1962"},{"key":"8_CR3","volume-title":"\u201eSUPREM: \u00c4 Program for IC Process Modeling and Simulators","author":"D \u00c4ntoniadis","year":"1977","unstructured":"D. \u00c4ntoniadis et al., \u201eSUPREM: \u00c4 Program for IC Process Modeling and Simulators\u201c, Stanford Electron Labs., May 1977, SEL-77\u2013006"},{"key":"8_CR4","series-title":"NATO Advanced Study Inst. Series E","volume-title":"Process and Device Modeling for Integrated Circuits","author":"F Wiele van de","year":"1977","unstructured":"F. van de Wiele, W. Engl, P. Jespers, \u201eProcess and Device Modeling for Integrated Circuits\u201c, NATO Advanced Study Inst. Series E, Noordhoft, Leyden, 1977"},{"key":"8_CR5","volume-title":"Numerical Analysis of Semiconductor Devices","author":"BT Browne","year":"1979","unstructured":"B. T. Browne, J. J. H. Miller, \u201eNumerical Analysis of Semiconductor Devices\u201c, Boole Press, Dublin, 1979"},{"key":"8_CR6","unstructured":"W. Engl et al., \u201eOSSI \u2014 One Dimensional Semiconductor Device Simulation\u201c, Inst. Theoret. Elektrotechnik, TH Aachen"},{"key":"8_CR7","unstructured":"S. Selberherr, A. Sch\u00fctz, H. P\u00f6tzl, \u201eMINIMOS \u2014 Twodimensional Modeling of MOS- Transistors\u201c, Inst, f\u00fcr Allgem. Elektrot. und Elektronik, A-1040 Wien, Gu\u00dfhausstra\u00dfe"},{"key":"8_CR8","unstructured":"\u201eTWODIM: Physical Simulation of Twodimensional Bipolar structures\u201c, LISCO, Kard. Mercierlaan 94, B-3030 Heverlee, Belgium"},{"key":"8_CR9","series-title":"Electronics Research Labs., Report No. ERL-M520","volume-title":"SPICE 2: A Computer Program to Simulate Semiconductor Circuits","author":"L Nagel","year":"1975","unstructured":"L. Nagel, \u201eSPICE 2: A Computer Program to Simulate Semiconductor Circuits\u201c, Electronics Research Labs., Report No. ERL-M520, University of California, Berkeley, Mai 1975"},{"key":"8_CR10","unstructured":"T. R\u00fcbner-Peterson, \u201eNAP 2: A nonlinear Analysis Program for Electronic Circuits\u201c, User Manual 16\/5\u201373, Inst. Circ. Theor. Telecomm., Technical University of Denmark, Lyngby"},{"key":"8_CR11","unstructured":"H. Levin et al., \u201eLASAR \u2014 Logic Automated Stimulus And Response\u201c, Teradyne Inc., 183 Essex Street, Boston, MA 02111"},{"key":"8_CR12","unstructured":"S. Szygenda et al., \u201eTEGAS\u201c, Comprehensive Computing Systems and Services, Austin, Texas"},{"key":"8_CR13","doi-asserted-by":"crossref","unstructured":"B. R. Chawla et al., \u201eMOTIS \u2014 A MOS Timing Simulator\u201c, IEEE Trans. Circ. Syst., Vol. CAS-22, 1975","DOI":"10.1109\/TCS.1975.1084003"},{"key":"8_CR14","volume-title":"MOTIS-C: A New Circuit Simulator for MOS LSI Circuits","author":"J Crawford","year":"1978","unstructured":"J. Crawford et al., \u201eMOTIS-C: A New Circuit Simulator for MOS LSI Circuits\u201c, Electronics Research Labs., University of California, Berkeley, 1978"},{"key":"8_CR15","series-title":"Electronics Research Lab., Report No. ERL-M78\/13","volume-title":"SIMPIL \u2014 Simulation Program for Injection Logic","author":"GR Boyle","year":"1978","unstructured":"G. R. Boyle, \u201eSIMPIL \u2014 Simulation Program for Injection Logic\u201c, Electronics Research Lab., Report No. ERL-M78\/13, University of California, Berkeley, 1978"},{"key":"8_CR16","unstructured":"G. Arnout et al., \u201eDIANA: A Digital Analog Timing Simulator\u201c, LISCO, Kard. Mercierlaan 94, B-3030 Heverlee, Belgium"},{"key":"8_CR17","series-title":"Electronics Research Lab., Report No. ERL M78\/52","volume-title":"SPLICE: The Simulation of Large Scale Integrated Circuits","author":"R Newton","year":"1978","unstructured":"R. Newton, \u201eSPLICE: The Simulation of Large Scale Integrated Circuits\u201c, Electronics Research Lab., Report No. ERL M78\/52, University of California, Berkeley, 1978"},{"key":"8_CR18","first-page":"255","volume-title":"Efficient Simulation of AHPL","author":"Z Navabi","year":"1979","unstructured":"Z. Navabi, F. J. Hill, \u201eEfficient Simulation of AHPL\u201c, Proc. of 16th Design Automation Conf., San Diego, S. 255, 1979"},{"key":"8_CR19","doi-asserted-by":"publisher","first-page":"850","DOI":"10.1109\/TC.1968.229145","volume":"C-17","author":"IR Duley","year":"1968","unstructured":"I. R. Duley, D. L. Dietmeyer, \u201eA Digital System Languages (DDL)\u201c, IEEE Trans. on Comp., Vol. C-17, S. 850, 1968","journal-title":"IEEE Trans. on Comp."},{"key":"8_CR20","first-page":"377","volume-title":"A Hierarchical Language for Structural Description of Digital Systems","author":"WM Cleemput Van","year":"1977","unstructured":"W. M. Van Cleemput, \u201eA Hierarchical Language for Structural Description of Digital Systems\u201c, Proc. 14th Design Automation Conf., San Francisco, S. 377, 1977"},{"key":"8_CR21","first-page":"115","volume-title":"Segmentation Constructs for RTS III","author":"R Piloty","year":"1975","unstructured":"R. Piloty, \u201eSegmentation Constructs for RTS III, \u201cProc. of 1975 Int. Symp. On Hardware Description Languages, New York, S. 115, 1975"},{"key":"8_CR22","unstructured":"M. Barbacci et al., \u201eThe ISP Computer Description Language\u201c, Dep. Comp. Sci., Carnegie-Mellon University"},{"key":"8_CR23","unstructured":"\u201eAGS 860 \u2014 Applicon Graphic System\u201c, Applicon, Burlington, MA 01803"},{"key":"8_CR24","unstructured":"\u201eGDS 2 \u2014 Calma Graphic Data System\u201c, Calma, Sunnyvale, Ca. 94086"},{"key":"8_CR25","unstructured":"\u201eCADD S2 \u2014 Integrated Circuit Design\u201c, Computervision, Bedford, MA 01730"},{"key":"8_CR26","doi-asserted-by":"publisher","first-page":"613","DOI":"10.1109\/JSSC.1979.1051225","volume":"SC-14","author":"H Man De","year":"1979","unstructured":"H. De Man, \u201eComputer-Aided Design for Integrated Circuits: Trying to Bridge the Gap\u201c, IEEE J. Sol. State Circ., Vol. SC-14, S. 613, 1979","journal-title":"IEEE J. Sol. State Circ."},{"key":"8_CR27","unstructured":"H. Beke, W. Sansen, \u201eCALMOS \u2014 A Portable Software System for the Automatic and Interactive Layout of MOS LSI\u201c, LISC0, Kard. Mercierlaan 94, B-3030 Heverlee, Belgium"},{"key":"8_CR28","first-page":"399","volume-title":"LTX \u2014 A System for Directed Automatic Design of LSI","author":"G Persky","year":"1976","unstructured":"G. Persky et al., \u201eLTX \u2014 A System for Directed Automatic Design of LSI\u201c, Proc. Design Automation Conf., San Francisco, S. 399, 1976"},{"key":"8_CR29","unstructured":"\u201eGAELIC: Graphic Aided Engineering Layout of integrated Circuits\u201c, Compeda, Stevenage, Herts., England"},{"key":"8_CR30","series-title":"Electronics Research Lab., Report No. ERL M79\/80","volume-title":"CABBAGE \u2014 Symbolic Layout and Compaction of Integrated Circuits","author":"H Hsueh","year":"1979","unstructured":"H. Hsueh, \u201eCABBAGE \u2014 Symbolic Layout and Compaction of Integrated Circuits\u201c, Electronics Research Lab., Report No. ERL M79\/80, University of California, Berkeley, 1979"},{"key":"8_CR31","volume-title":"Das Layout-Kontrollsystem LOCATE","author":"U J\u00e4ger","year":"1979","unstructured":"U. J\u00e4ger, \u201eDas Layout-Kontrollsystem LOCATE\u201c, Halbleiterwerk AEG-TELEFUNKEN, Heilbronn, 1979"},{"key":"8_CR32","first-page":"322","volume-title":"Design Rule Checking and Analysis of IC-mask Designs","author":"BW Lindsay","year":"1977","unstructured":"B. W. Lindsay, B. T. Preas, \u201eDesign Rule Checking and Analysis of IC-mask Designs\u201c, Proc. Design Automation Conf., San Francisco, S. 322, 1977"},{"key":"8_CR33","first-page":"322","volume-title":"A Layout Checking System for Large Scale Integrated Circuits","author":"K Toshida","year":"1977","unstructured":"K. Toshida et al., \u201eA Layout Checking System for Large Scale Integrated Circuits\u201c, Proc. Design Automation Conf., San Francisco, S. 322, 1977"}],"container-title":["Informatik-Fachberichte","CAD-Fachgespr\u00e4ch"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-67839-4_8.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,24]],"date-time":"2020-11-24T22:10:21Z","timestamp":1606255821000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-67839-4_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1980]]},"ISBN":["9783540103899","9783642678394"],"references-count":33,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-67839-4_8","relation":{},"ISSN":["0343-3005"],"issn-type":[{"type":"print","value":"0343-3005"}],"subject":[],"published":{"date-parts":[[1980]]}}}