{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T17:50:12Z","timestamp":1725645012852},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540503606"},{"type":"electronic","value":"9783642741357"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1988]]},"DOI":"10.1007\/978-3-642-74135-7_7","type":"book-chapter","created":{"date-parts":[[2011,12,22]],"date-time":"2011-12-22T18:57:48Z","timestamp":1324580268000},"page":"106-118","source":"Crossref","is-referenced-by-count":0,"title":["Entwurf von Testarchitekturen f\u00fcr VLSI-Bausteine"],"prefix":"10.1007","author":[{"given":"Manfred","family":"Gerner","sequence":"first","affiliation":[]}],"member":"297","reference":[{"key":"7_CR1","first-page":"50","volume":"80","author":"H Ando","year":"1980","unstructured":"Ando, H.: Testing VLSI with Random Access Scan, Digest of Papers Compcon 80, 1980, S. 50\u201352","journal-title":"Digest of Papers Compcon"},{"key":"7_CR2","volume-title":"Fehlererkennung in kombinatorischen Schaltkreisen","author":"N Blum","year":"1985","unstructured":"Blum, N.: Fehlererkennung in kombinatorischen Schaltkreisen, Universit\u00e4t Saarbr\u00fccken, FB 10, SFB 124, Bericht 10\/1985"},{"key":"7_CR3","first-page":"98","volume-title":"On the acceleration of test generation algorithms","author":"H Fujiwara","year":"1983","unstructured":"Fujiwara, H.; Shimono, T.: On the acceleration of test generation algorithms, Proc. FTCS-13, 1983, S. 98\u2013105"},{"key":"7_CR4","volume-title":"Scan Path in CMOSSemicustom LSI Chips","author":"M Gerner","year":"1984","unstructured":"Gerner, M.; Nertinger, H.: Scan Path in CMOSSemicustom LSI Chips Proceedings IEEE Test Conference 1984"},{"key":"7_CR5","volume-title":"Qualitative Testability Analysis and Hierarchical Test Pattern","author":"M Gerner","year":"1987","unstructured":"Gerner, M.; Hofest\u00e4dt, H.: Qualitative Testability Analysis and Hierarchical Test Pattern Generation Proceedings IEEE Test Conference 1987, Washington"},{"key":"7_CR6","volume-title":"IEEE Computer","author":"D Gajski","year":"1983","unstructured":"Gajski, D.; Kuhn, R.: New VLSI Tools. IEEE Computer, Dezember 1983"},{"key":"7_CR7","volume-title":"IEEE Trans on Computers","author":"P Goel","year":"1981","unstructured":"Goel, P: An Implicit Enumeration Algorithm to Generate Tests for Combinatorial Logic Circuits, IEEE Trans, on Computers, 1981"},{"key":"7_CR8","volume-title":"IEEE Trans on Circuits&Systems","author":"LH Goldstein","year":"1979","unstructured":"Goldstein, L. H.: Controllabilty]Observability Analysis of digital Circuits, IEEE Trans on Circuits&Systems, Vol. LAS-26, No. 9, 1979"},{"key":"7_CR9","volume-title":"Advances in CAD for VLSI","author":"S Goto","year":"1986","unstructured":"Goto, S: Design Methodologies in: Advances in CAD for VLSI, Volume 6, 1986, North-Holland"},{"key":"7_CR10","first-page":"333","volume-title":"The GENESYS-aigorithm for ATPG without fault simulation","author":"M Johansson","year":"1983","unstructured":"Johansson, M.: The GENESYS-aigorithm for ATPG without fault simulation, Proc. International Test Conference, 1983, S. 333\u2013337"},{"key":"7_CR11","first-page":"37","volume-title":"Built-in Logic Block Observation Technique","author":"B Konemann","year":"1979","unstructured":"Konemann, B.; Mucha, J., Zwiehoff, G.: Built-in Logic Block Observation Technique, Digest 1979 Int\u2019l Test Conf., 1979, S. 37\u201341"},{"key":"7_CR12","volume-title":"Integration, VLSI journal","author":"M Renovell","year":"1985","unstructured":"Renovell, M.;Cambon, G.; Auvergne, D.:FSPICE: a tool for fault modelling in MOS circuits, Integration, VLSI journal 3 1985, North Holland"},{"key":"7_CR13","first-page":"13","volume-title":"IEEE Design & Test","author":"JP Shen","year":"1985","unstructured":"Shen, J. P., Maly W., Ferguson, F. J.: Inductive Fault Analysis of MOS-Integrated Circuits, IEEE Design & Test, Dez. 1985, S. 13\u201326"},{"key":"7_CR14","volume-title":"IEEE trans on computers","author":"DS Suk","year":"1981","unstructured":"Suk, D. S.; Reddy, S. M.: A March Test for Functional faults in Semiconductor Random Access Memories, IEEE trans on computers, 1981"},{"unstructured":"Vogt, M; Hofest\u00e4dt, H: Wertebereichsanalyse zur Unterst\u00fctzung einer hierarchischen Testmustergenerierung, im vorliegenden Tagungsband","key":"7_CR15"},{"unstructured":"Winter, Th: Ein Ansatz zur hierarchischen Testvorbereitung f\u00fcr sequentielle Schaltungen, im vorliegenden Tagungsband","key":"7_CR16"}],"container-title":["Informatik-Fachberichte","GI \u2014 18. Jahrestagung II"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-74135-7_7.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,6]],"date-time":"2021-05-06T12:40:57Z","timestamp":1620304857000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-74135-7_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1988]]},"ISBN":["9783540503606","9783642741357"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-74135-7_7","relation":{},"ISSN":["0343-3005"],"issn-type":[{"type":"print","value":"0343-3005"}],"subject":[],"published":{"date-parts":[[1988]]}}}