{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T15:14:09Z","timestamp":1725635649014},"publisher-location":"Berlin, Heidelberg","reference-count":5,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540515654"},{"type":"electronic","value":"9783642750021"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1989]]},"DOI":"10.1007\/978-3-642-75002-1_30","type":"book-chapter","created":{"date-parts":[[2011,11,19]],"date-time":"2011-11-19T00:16:14Z","timestamp":1321661774000},"page":"368-378","source":"Crossref","is-referenced-by-count":2,"title":["Efficiency of Self-Test Path as a Test Pattern Generator and Test Response Compactor"],"prefix":"10.1007","author":[{"given":"Dariusz","family":"Badura","sequence":"first","affiliation":[]}],"member":"297","reference":[{"key":"30_CR1","unstructured":"A Test Access Port and Boundary-Scan Architecture, Joint Test Action Group, Third published version, April 1988."},{"key":"30_CR2","first-page":"165","volume-title":"Universal Test Controller Chip for Board Self-Test","author":"A Hlawiczka","year":"1987","unstructured":"A. Hlawiczka, D. Badura: Universal Test Controller Chip for Board Self-Test, Proc. of FTCS \u201987, Bremerhaven, September 1987, pp. 165\u2013175."},{"key":"30_CR3","unstructured":"L.T. Wang, E. McCluskey: A Hybrid Design of Maximum-Length Sequence Generators, Proc. of ITC, 1986, pp. 38\u201345."},{"key":"30_CR4","unstructured":"A. Krasniewski, S. Pilarski: Effectiveness of Using a Test Response Compactor for Test Pattern Generation, Proc. of 10th Int. Conf. FTS&D \u201987, Varna 1987, pp. 284\u2013289."},{"key":"30_CR5","unstructured":"A. Krasniewski, S. Pilarski: Experiments with Test Pattern Generation Using a Test Response Compactor, Proc. of 11th Int Conf. FTS&D \u201988, Suhl 1988, pp. 197\u2013202."}],"container-title":["Informatik-Fachberichte","Fehlertolerierende Rechensysteme \/ Fault-tolerant Computing Systems"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-75002-1_30.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,25]],"date-time":"2020-11-25T02:20:55Z","timestamp":1606270855000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-75002-1_30"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1989]]},"ISBN":["9783540515654","9783642750021"],"references-count":5,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-75002-1_30","relation":{},"ISSN":["0343-3005"],"issn-type":[{"type":"print","value":"0343-3005"}],"subject":[],"published":{"date-parts":[[1989]]}}}