{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,15]],"date-time":"2025-03-15T04:12:15Z","timestamp":1742011935596,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540545453"},{"type":"electronic","value":"9783642769306"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1991]]},"DOI":"10.1007\/978-3-642-76930-6_12","type":"book-chapter","created":{"date-parts":[[2011,11,21]],"date-time":"2011-11-21T06:05:29Z","timestamp":1321855529000},"page":"136-147","source":"Crossref","is-referenced-by-count":2,"title":["Emulation of Scan Paths in Sequential Circuit Synthesis"],"prefix":"10.1007","author":[{"given":"Bernhard","family":"Eschermann","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"12_CR1","doi-asserted-by":"crossref","unstructured":"V. Agrawal, K. Cheng: FSM Synthesis with Embedded Test Function; JETTA, pp. 212\u2013228, 1990.","DOI":"10.1007\/BF00153859"},{"key":"12_CR2","first-page":"1062","volume":"6","author":"R Brayton","year":"1987","unstructured":"R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, Albert R. Wang: MIS: A Multiple-Level Logic Optimization System; IEEE Trans, on CAD, vol. 6, pp. 1062\u20131081, 1987.","journal-title":"Wang: MIS: A Multiple-Level Logic Optimization System; IEEE Trans, on CAD"},{"key":"12_CR3","doi-asserted-by":"crossref","unstructured":"K. Cheng, V. Agrawal: Design of Sequential Machin\u00e9s for Efficient Test Generation; Dig. Tech. Papers ICCAD, pp. 358\u2013361, 1989.","DOI":"10.1109\/ICCAD.1989.76969"},{"key":"12_CR4","first-page":"28","volume":"19","author":"K Cheng","year":"1989","unstructured":"K. Cheng, V. Agrawal: An Economical Scan Design for Sequential Logic Test Generation; Proc. FTCS 19, pp. 28\u201335, 1989.","journal-title":"FTCS"},{"key":"12_CR5","volume-title":"Christofides: Graph Theory: An Algorithmic Approach","author":"N Christofides","year":"1975","unstructured":"N. Christofides: Graph Theory: An Algorithmic Approach; Academic Press, London, 1975."},{"key":"12_CR6","first-page":"8","volume":"9","author":"HT Dcvadas","year":"1990","unstructured":"S. Dcvadas, H. T. Ma, A. R. Newton, A. Sangiovanni-Vincentelli: Irredundant Sequential Machines Via Optimal Logic Synthesis; IEEE Trans, on CAD, vol. 9, pp. 8\u201318, 1990.","journal-title":"Irredundant Sequential Machines Via Optimal Logic Synthesis; IEEE Trans, on CAD"},{"key":"12_CR7","unstructured":"B. Eschermann, H.-J. Wunderlich: A Synthesis Approach to Reduce Scan Design Overhead; Proc. 1st EDAC, p. 671, 1990."},{"key":"12_CR8","volume-title":"Computers and Intractability","author":"M Garey","year":"1979","unstructured":"M. Garey, D. Johnson: Computers and Intractability; Freeman, New York 1979."},{"key":"12_CR9","doi-asserted-by":"crossref","unstructured":"P. Goel: Test Generation Costs Analysis and Projections; Proc. 17th DAC, pp. 77\u201384,1980","DOI":"10.1145\/800139.804515"},{"key":"12_CR10","doi-asserted-by":"crossref","unstructured":"F. C. Hennie: Fault Detecting Experiments for Sequential Circuits; Proc. 5th Annual Symp. Switching Circuit Theory and Logical Design, pp. 95\u2013110, 1964.","DOI":"10.1109\/SWCT.1964.8"},{"key":"12_CR11","unstructured":"IEEE Std. PI 149.1: Standard Test Access Port and Boundary-Scan Architecture, 1990."},{"key":"12_CR12","first-page":"163","volume":"1","author":"A Kunzmann","year":"1990","unstructured":"A. Kunzmann, H.-J. Wunderlich: An Analytical Approach to the Partial Scan Problem; JETTA, vol. 1, pp. 163\u2013174, 1990.","journal-title":"An Analytical Approach to the Partial Scan Problem; JETTA"},{"key":"12_CR13","volume-title":"New York","author":"E Lawler","year":"1976","unstructured":"E. Lawler: Combinatorial Optimization: Networks and Matroids; Holt, New York, 1976."},{"key":"12_CR14","unstructured":"Logic Synthesis and Optimization Benchmarks, Version 2.0; MCNC, December 1988."}],"container-title":["Informatik-Fachberichte","Fault-Tolerant Computing Systems"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-76930-6_12.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,14]],"date-time":"2025-03-14T07:45:12Z","timestamp":1741938312000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-76930-6_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1991]]},"ISBN":["9783540545453","9783642769306"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-76930-6_12","relation":{},"ISSN":["0343-3005"],"issn-type":[{"type":"print","value":"0343-3005"}],"subject":[],"published":{"date-parts":[[1991]]}}}