{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,5]],"date-time":"2025-04-05T22:40:09Z","timestamp":1743892809693,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540531630"},{"type":"electronic","value":"9783642843044"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1990]]},"DOI":"10.1007\/978-3-642-84304-4_15","type":"book-chapter","created":{"date-parts":[[2012,7,28]],"date-time":"2012-07-28T23:48:34Z","timestamp":1343519314000},"page":"169-181","source":"Crossref","is-referenced-by-count":0,"title":["Zum automatischen Einf\u00fcgen von Testpunkten in sequentielle Schaltungen"],"prefix":"10.1007","author":[{"given":"H.","family":"Gundlach","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K. -D.","family":"M\u00fcller-Glaser","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"15_CR1","volume-title":"Data structures and algorithms","author":"AV Aho","year":"1983","unstructured":"Aho, A.V.: Data structures and algorithms.. Addison-Wesley series in computer science and information processing, London, 1983."},{"key":"15_CR2","doi-asserted-by":"crossref","unstructured":"Agrawal, V.D.; Cheng, K.-T.; Johnson, D.D. und Tonysheng L.: Designing Circuits with Partial Scan. IEEE Design Sc Test of Computers, S. 8\u201315, April 1988.","DOI":"10.1109\/54.2032"},{"key":"15_CR3","volume-title":"Combinational Profiles of Sequential Benchmark Circuits","author":"F Brglez","year":"1989","unstructured":"Brglez, F.; Bryan, D. and Kozminski, K.: Combinational Profiles of Sequential Benchmark Circuits. Proc. IEEE ISCAS, 1989."},{"key":"15_CR4","doi-asserted-by":"crossref","unstructured":"Cheng, K.-T. und Agrawal, V.D.: An Economical Scan Design for Sequential Logic Test Generation. FTCS, S. 28\u201335, 1989.","DOI":"10.1109\/FTCS.1989.105539"},{"key":"15_CR5","doi-asserted-by":"crossref","DOI":"10.7551\/mitpress\/4317.001.0001","volume-title":"Logic Testing and Design for Testability. Computer Science Series, The MIT Press","author":"H Fujiwara","year":"1985","unstructured":"Fujiwara, H.: Logic Testing and Design for Testability. Computer Science Series, The MIT Press, Cambridge, Massachusetts, 1985."},{"key":"15_CR6","volume-title":"Computers and Intractability: A Guide to the Theory of NP-completeness. W.H","author":"MR Garey","year":"1979","unstructured":"Garey, M.R.; Johnson, D.S.: Computers and Intractability: A Guide to the Theory of NP-completeness. W.H. Freemann & Company, San Francisco 1979."},{"issue":"1","key":"15_CR7","first-page":"77","volume":"4","author":"Johnson","year":"1975","unstructured":"Johnson, D.B.: Finding all the elementary circuits of a directed graph. SIAM J. Comput., Vol. 4, No. 1, S. 77\u201384, March 1975.","journal-title":"J. Comput."},{"key":"15_CR8","doi-asserted-by":"crossref","unstructured":"Kunzmann, A.: Produktionstest synchroner Schaltwerke auf der Basis von Pipelinestrukturen. Proc. 18. GI-Jahrestagung, Springer, Berlin, S. 92\u2013105, 1988.","DOI":"10.1007\/978-3-642-74135-7_6"},{"key":"15_CR9","volume-title":"Intelligen documentation package","author":"HHB","year":"1989","unstructured":"HHB: Intelligen documentation package. Mahwah, New Jersey, 1989."},{"key":"15_CR10","volume-title":"EX TEST: Ein regelbasiertes System zur Unterst\u00fctzung des Entwurfs gut testbarer, digitaler, hochintegrierter Schaltungen","author":"C Matth\u00e4us","year":"1988","unstructured":"Matth\u00e4us, C.: EX TEST: Ein regelbasiertes System zur Unterst\u00fctzung des Entwurfs gut testbarer, digitaler, hochintegrierter Schaltungen. Ges. f\u00fcr Mathematik und Datenverarbeitung mbH, Sankt Augustin, 1988."},{"key":"15_CR11","volume-title":"Zur Verbesserung der Testbarkeit digitaler Schaltungen","author":"C Sandmeier","year":"1989","unstructured":"Sandmeier, C.: Zur Verbesserung der Testbarkeit digitaler Schaltungen. Diploma thesis at \u201cLehrstuhl f\u00fcr rechnergest\u00fctztes Entwerfen\u201d, Universit\u00e4t M\u00fcnchen, 1989."},{"key":"15_CR12","doi-asserted-by":"publisher","first-page":"1198","DOI":"10.1109\/TC.1983.1676183","volume":"12","author":"Savir","year":"1983","unstructured":"Savir, J.: Good Controllability and Observability Do Not Guarantee Good Testability. IEEE Trans. on Computers, Vol. C-32,No. 12, S. 1198\u20131200, Dec. 1983.","journal-title":"IEEE Trans. on Computers, Vol. C-32"},{"key":"15_CR13","volume-title":"Fehlerlokalisierung in Digitalschaltungen mit Hilfe des Aquivalenzklassenverfahrens","author":"J Schl\u00e4per","year":"1976","unstructured":"Schl\u00e4per, J.: Fehlerlokalisierung in Digitalschaltungen mit Hilfe des Aquivalenzklassenverfahrens. Dissertation an der Fakult\u00e4t der Elektrotechnik der Rheinisch-Westf\u00e4lische Technische Hochschule, Aachen 1976."},{"key":"15_CR14","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-642-73910-1","volume-title":"Testmustergenerierung und Fehlersimulation in digitalen Schaltungen mit hoher Komplexit\u00e4t, Informatik-Fachberichte","author":"MH Schulz","year":"1988","unstructured":"Schulz, M.H.: Testmustergenerierung und Fehlersimulation in digitalen Schaltungen mit hoher Komplexit\u00e4t, Informatik-Fachberichte 173. Springer Verlag, Heidelberg, 1988."},{"key":"15_CR15","first-page":"190","volume":"4","author":"K Totton","year":"1988","unstructured":"Totton, K. and Shan, S.: Self-test: the solution to the VLSI test problem ?. IEE Proceedings, Vol 135, Pt. E, Nr 4, S. 190\u2013195, July 1988.","journal-title":"E, Nr"},{"key":"15_CR16","volume-title":"LSI\/VLSI Testability Design","author":"FF Tsui","year":"1987","unstructured":"Tsui, F. F.: LSI\/VLSI Testability Design. MCGraw-Hill Book Company, New York, 1987."},{"key":"15_CR17","doi-asserted-by":"crossref","unstructured":"Wunderlich, H.-J. and Hellebrand, S.: The Pseudo-Exhaustive Test of Sequential Circuits. ITC, S. 19\u201327, 1989.","DOI":"10.1109\/TEST.1989.82273"}],"container-title":["Rechnergest\u00fctzter Entwurf und Architektur mikroelektronischer Systeme"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-84304-4_15.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,5]],"date-time":"2025-04-05T22:27:40Z","timestamp":1743892060000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-84304-4_15"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1990]]},"ISBN":["9783540531630","9783642843044"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-84304-4_15","relation":{},"subject":[],"published":{"date-parts":[[1990]]}}}