{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T07:55:43Z","timestamp":1725695743872},"publisher-location":"Berlin, Heidelberg","reference-count":30,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540531630"},{"type":"electronic","value":"9783642843044"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1990]]},"DOI":"10.1007\/978-3-642-84304-4_18","type":"book-chapter","created":{"date-parts":[[2012,7,28]],"date-time":"2012-07-28T19:48:34Z","timestamp":1343504914000},"page":"207-220","source":"Crossref","is-referenced-by-count":0,"title":["KOSIM \u2014 ein Mixed-Mode, Multi-Level-Simulator"],"prefix":"10.1007","author":[{"given":"P.","family":"Schwarz","sequence":"first","affiliation":[]},{"given":"C.","family":"Clau\u00df","sequence":"additional","affiliation":[]},{"given":"U.","family":"Donath","sequence":"additional","affiliation":[]},{"given":"J.","family":"Haufe","sequence":"additional","affiliation":[]},{"given":"G.","family":"Kurth","sequence":"additional","affiliation":[]},{"given":"P.","family":"Trappe","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"issue":"3","key":"18_CR1","doi-asserted-by":"crossref","first-page":"326","DOI":"10.1109\/JSSC.1978.1051048","volume":"13","author":"G. Arnout","year":"1978","unstructured":"Arnout, G.; DeMan, H.: The use of threshold functions and boolean-controlled network elements for macromodelling of LSI circuits. IEEE J. Solid-State Circuits SC-13(1978)3, 326-332","journal-title":"IEEE J. Solid-State Circuits SC-"},{"key":"18_CR2","doi-asserted-by":"crossref","DOI":"10.1007\/978-94-011-8006-1","volume-title":"Computer Design Aids for VLSI Circuits","author":"P Antognetti","year":"1981","unstructured":"Antognetti, P.; Pederson, D.O.; DeMan, H.: Computer Design Aids for VLSI Circuits. Sijthoff Nordhoff, Alphen 1981"},{"key":"18_CR3","volume-title":"F. Anceau, E.J. Aas (Hrg.) VLSI83; North-Holland","author":"D Borrione","year":"1983","unstructured":"Borrione, D.; Humbert, M.; Le Faou, C.: Hierarchical mixed-mode simulation mechanisms in the CASCADE project. In: F. Anceau, E.J. Aas (Hrg.) VLSI\u201983; North-Holland 1983"},{"key":"18_CR4","unstructured":"Breuer, M.A. (Hrg.): Digital System Design Automation: Languages, Simulation Data Bases.Computer Science Press,1975"},{"key":"18_CR5","first-page":"26","volume-title":"A survey of switch-level algorithms","author":"RE Bryant","year":"1987","unstructured":"Bryant, R.E.: A survey of switch-level algorithms. IEEE Design Test, August 1987, 26\u201340"},{"key":"18_CR6","first-page":"75","volume-title":"Einige Aspekte der Implementierung und Anwendung der Hardware-beschreibungssprache ISPS. 16","author":"U Crenze","year":"1988","unstructured":"Crenze, U.: Einige Aspekte der Implementierung und Anwendung der Hardware-beschreibungssprache ISPS. 16. ZKI-Arbeitstagung, Dresden 1988, 75\u201379"},{"key":"18_CR7","unstructured":"Clau\u00df, C.; Schwarz, P.: Ein Verfahren zur blockorientierten Analyse nicht-linearer Netzwerke. 3. Tagung Schaltkreisentwurf, Dresden 1989, 153-157"},{"issue":"9","key":"18_CR8","doi-asserted-by":"crossref","first-page":"850","DOI":"10.1109\/TC.1968.229145","volume":"-17","author":"J.R. Duley","year":"1968","unstructured":"Duley, J.R.; Dietmeyer, D.L.: A digital system design language (DDL). IEEE Trans. Computer C-17(1968)9, 850\u2013861","journal-title":"IEEE Trans. Computer C"},{"key":"18_CR9","unstructured":"DACAPO III System, User Manual. Dosis GmbH, Dortmund 1987"},{"issue":"1","key":"18_CR10","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1109\/TCAD.1982.1269994","volume":"1","author":"H.W. Daseking","year":"1982","unstructured":"Daseking, H.W.; Gardner, R.I.; Weil, P.B.: VISTA: a VLSI CAD system. IEEE Trans. CAD-1(1982)1, 36\u201352","journal-title":"IEEE Trans. CAD-"},{"key":"18_CR11","first-page":"201","volume-title":"Behandlung von MOS-Schaltungen in der dynamischen Logiksimulation. 3","author":"U Donath","year":"1989","unstructured":"Donath, U.: Behandlung von MOS-Schaltungen in der dynamischen Logiksimulation. 3. Tagung Schaltkreisentwurf, Dresden 1989, 201\u2013205"},{"key":"18_CR12","first-page":"24","volume-title":"THEMIS logic simulator - a mixed mode, multi-level, hierarchical, interactive digital circuit simulator. Proc. 21","author":"MH Doshi","year":"1984","unstructured":"Doshi, M.H.; Sullivan, R.B.; Schuler, D.M.: THEMIS logic simulator\u2013a mixed mode, multi-level, hierarchical, interactive digital circuit simulator. Proc. 21. Design Autom. Conf. 1984, 24\u201331"},{"key":"18_CR13","first-page":"218","volume-title":"Dynamische Logiksimulation auf Bit-und Wort-Niveau. 1","author":"U Donath","year":"1986","unstructured":"Donath, U.; Schwarz, P.; Trappe, P.: Dynamische Logiksimulation auf Bit-und Wort-Niveau. 1. Tagung Schaltkreisentwurf, TU Dresden 1986, 218\u2013228"},{"key":"18_CR14","unstructured":"Donath, U.; Schwarz, P.; Trappe, P.; Clauss, C.; Kurth, G.: A multi-level simulator for integrated circuit design. Proc. ECCTD\u201987, Paris 1987, 465\u2013470"},{"key":"18_CR15","first-page":"58","volume-title":"Gate-Array-Schaltkreise f\u00fcr den Satellitenrundfunk. 16","author":"FE Engelmann","year":"1988","unstructured":"Engelmann, F.E.; Sch\u00e4ffer, D.; S\u00fchnel, C.: Gate-Array-Schaltkreise f\u00fcr den Satellitenrundfunk. 16. ZKI-Arbeitstagung, Dresden 1988, 58\u201362"},{"key":"18_CR16","unstructured":"Goering, R.: A full range of solutions emerge to handle mixed-mode simulation. Computer Design (1988)3, 57\u201365"},{"key":"18_CR17","first-page":"122","volume-title":"HBD - Ein Programmsystem zur Simulation von Struktur und Funktion komplexer digitaler Systeme","author":"D Garte","year":"1989","unstructured":"Garte, D.; Haufe, J.; RUlke, S.: HBD\u2013Ein Programmsystem zur Simulation von Struktur und Funktion komplexer digitaler Systeme. 3. Tagung Schaltkreisentwurf, Dresden 1989, 122\u2013127"},{"key":"18_CR18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-82573-6","volume-title":"Simulation elektrischer Schaltungen auf dem Rechner","author":"E-H Horneber","year":"1985","unstructured":"Horneber, E.-H.: Simulation elektrischer Schaltungen auf dem Rechner. Springer, Berlin 1985"},{"key":"18_CR19","unstructured":"Issel, W. u.a.: NBS-84: A structural description language for VLSI design. Proc ECCTD\u201985, Prag 1985, 62\u201365"},{"key":"18_CR20","unstructured":"Kurth, G.; Trappe, P.: Ein Programmsystem zur multi-level-Simulation integrierter Schaltkreise. 32. Intern. Wiss. Koll. TH Ilmenau 1987, Sektion B2, 207\u2013210"},{"key":"18_CR21","first-page":"23","volume-title":"Aspekte des funktionellen und strukturellen Gate-Array-Entwurfs auf PC-Technik. 3","author":"D M\u00fcller","year":"1989","unstructured":"M\u00fcller, D.; Knoth, U.; Zimmermannn, C.: Aspekte des funktionellen und strukturellen Gate-Array-Entwurfs auf PC-Technik. 3. Tagung Schaltkreisentwurf, Dresden 1989, 23\u201327"},{"key":"18_CR22","unstructured":"Muller, J.; Lattermann, J.: PASHDL - Eine Moeglichkeit zur funktionellen Hardware-Beschreibung. Wiss. Z. TU Dresden (1989), Heft 1"},{"key":"18_CR23","doi-asserted-by":"crossref","first-page":"741","DOI":"10.1109\/TCS.1979.1084694","volume":"-26","author":"A.R. Newton","year":"1979","unstructured":"Newton, A.R.: Techniques for the simulation of large-scale integrated circuits. IEEE-Trans. CAS-26(1979)9,741\u2013749","journal-title":"IEEE-Trans. CAS"},{"key":"18_CR24","doi-asserted-by":"crossref","first-page":"308","DOI":"10.1109\/TCAD.1984.1270089","volume":"3","author":"A.R. Newton","year":"1984","unstructured":"Newton, A.R.; Sangiovanni-Vincentelli, A.L.: Relaxation-based electrical simulation. IEEE Trans.CAD-3(1984)4,308\u2013330","journal-title":"IEEE Trans.CAD-"},{"key":"18_CR25","unstructured":"Oberst,E.; W\u00e4chter,F.: Erarbeitung des funktionellen Verst\u00e4ndnisses eines Schaltkreises durch Modellierung und Simulation. 16. ZKI-Arbeitstagung, Dresden 1988, 67\u201370"},{"key":"18_CR26","unstructured":"Rammig, F.J.: Multilevel simulation techniques. Proc. COMPEURO\u201987"},{"key":"18_CR27","unstructured":"Reynaert, Ph.; De Man, H. et al.: DIANA: a mixed-mode simulator with a hardware description language for hierarchical design of VLSI. Proc. ICCC 1980, 356-360"},{"key":"18_CR28","volume-title":"Prag","author":"P Schwarz","year":"1985","unstructured":"Schwarz,P.: KOSIM - A program for the mixed-level simulation of digital integrated circuits. Proc. ECCTD\u201985, Prag 1985"},{"key":"18_CR29","first-page":"139","volume-title":"Iterated timing analysis","author":"RA Saleh","year":"1983","unstructured":"Saleh, R.A.; Kleckner, J.E.; Newton, A.R.: Iterated timing analysis. Proc. ICCAD, Sept. 1983, 139\u2013140"},{"key":"18_CR30","volume-title":"ZKI-Forschungsbericht","author":"U Donath","year":"1989","unstructured":"Donath, U.: Simulation zeitbewerteter Petri-Netze mit dem Multi-LevelSimulator KOSIM. ZKI-Forschungsbericht, 1989"}],"container-title":["Rechnergest\u00fctzter Entwurf und Architektur mikroelektronischer Systeme"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-84304-4_18.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,26]],"date-time":"2020-11-26T20:55:10Z","timestamp":1606424110000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-84304-4_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1990]]},"ISBN":["9783540531630","9783642843044"],"references-count":30,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-84304-4_18","relation":{},"subject":[],"published":{"date-parts":[[1990]]}}}