{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T07:56:40Z","timestamp":1725695800701},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540531630"},{"type":"electronic","value":"9783642843044"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1990]]},"DOI":"10.1007\/978-3-642-84304-4_3","type":"book-chapter","created":{"date-parts":[[2012,7,28]],"date-time":"2012-07-28T23:48:34Z","timestamp":1343519314000},"page":"24-32","source":"Crossref","is-referenced-by-count":2,"title":["HIPARE: Hierarchical Circuit and Parameter Extraction from Mask Layout Data"],"prefix":"10.1007","author":[{"given":"U.","family":"R\u00f6ttcher","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Fritz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Krohm","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Hess","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"3_CR1","doi-asserted-by":"crossref","unstructured":"S.P. McCormick, \u201cEXCL: A Circuit Extractor for IC Designs,\u201d Proc. 21st Design Automation Conference, pp. 616\u2013623, Jun. 1984.","DOI":"10.1109\/DAC.1984.1585863"},{"key":"3_CR2","doi-asserted-by":"crossref","unstructured":"W.S. Scott, J.K. Ousterhout, \u201cMagic\u2019s Circuit Extractor,\u201d Proc. 22nd Design Automation Conference, pp. 286\u2013292, Jun. 1985.","DOI":"10.1109\/DAC.1985.1585954"},{"key":"3_CR3","unstructured":"V. Henkel, U.Golze, \u201cRISCE - A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification Based on Interaction Rules,\u201d Proc. Conf. CICC, 1988."},{"key":"3_CR4","doi-asserted-by":"crossref","unstructured":"Y. Wong, \u201cHierarchical Circuit Verification,\u201d Proc. 22nd Design Automation Conf, pp. 695\u2013701, 1985.","DOI":"10.1145\/317825.317965"},{"key":"3_CR5","doi-asserted-by":"crossref","unstructured":"T.J. Wagner, \u201cHierarchical Layout Verification,\u201d Proc. 21st Design Automation Conf, pp. 484\u2013489, 1984.","DOI":"10.1109\/DAC.1984.1585842"},{"key":"3_CR6","doi-asserted-by":"crossref","unstructured":"G.M. Tarolli, W.J. Herman, \u201cHierachical Circuit Extraction with Detailed Parasitic Capacitance,\u201d Proc. 20th Design Automation Conf, pp. 337\u2013345, 1983.","DOI":"10.1109\/DAC.1983.1585671"},{"key":"3_CR7","unstructured":"S.C. Johnson, \u201cHierarchical Design Validation Based on Rectangles,\u201d Proc. Conf. on Advanced Research in VLSI, pp. 97\u2013100, 1982."},{"key":"3_CR8","doi-asserted-by":"crossref","unstructured":"A. Bootehsaz, R.A. Courel, \u201cA Technology Independent Approach to Hierarchical IC Layout Extraction,\u201d Proc. 23rd Design Automation Conf, pp. 425\u2013431, 1986.","DOI":"10.1109\/DAC.1986.1586124"},{"issue":"1","key":"3_CR9","doi-asserted-by":"crossref","first-page":"66","DOI":"10.1109\/MDT.1986.294941","volume":"3","author":"Louis K. Scheffer","year":"1986","unstructured":"L.K. Scheffer, R. Soetarman, \u201cHierarchical Analysis of IC Artwork with User-Defined Rules,\u201d IEEE Design & Test, pp. 66\u201374, 1986.","journal-title":"IEEE Design & Test of Computers"},{"key":"3_CR10","doi-asserted-by":"crossref","unstructured":"U. Lauther, \u201cAn O(N log N) Algorithm fcr Boolean Mask Operations,\u201d Proc. 18th Design Automation Conference, pp. 555\u2013562, Jun. 1981.","DOI":"10.1109\/DAC.1981.1585410"},{"issue":"9","key":"3_CR11","doi-asserted-by":"publisher","first-page":"643","DOI":"10.1109\/TC.1979.1675432","volume":"C-28","author":"JL Bentley","year":"1979","unstructured":"J.L. Bentley, T.A. Ottmann, \u201cAlgorithms for Reporting and Counting Geometric Intersections,\u201d IEEE Transactions on Computers, VOL. C-28, NO. 9, pp. 643\u2013647, Sept. 1979.","journal-title":"IEEE Transactions on Computers"},{"issue":"2","key":"3_CR12","doi-asserted-by":"publisher","first-page":"183","DOI":"10.1109\/T-ED.1983.21093","volume":"ED-30","author":"T Sakurai","year":"1983","unstructured":"T. Sakurai, K. Tamaru, \u201cSimple Formulas for Two-and Three-Dimensional Capacitances,\u201d IEEE Trans. on Electron Devices, Vol. ED-30, No. 2, pp. 183\u2013185, 1983.","journal-title":"IEEE Trans. on Electron Devices"},{"issue":"3","key":"3_CR13","first-page":"478","volume":"CAD-2","author":"M Horowitz","year":"1979","unstructured":"M. Horowitz, R.W. Dutton, \u201cResistance Extraction from Mask Layout Data\u201d, IEEE Trans. on CAD, Vol. CAD-2, No. 3, pp. 478\u2013481, 1979.","journal-title":"IEEE Trans. on CAD"},{"key":"3_CR14","doi-asserted-by":"crossref","unstructured":"J. Bentley, T. Ottmann, \u201cThe Complexity of Manipulating Hierarchically Defined Sets of Rectangles,\u201d Technical Report, Carnegie Mellon University, 1981.","DOI":"10.1007\/3-540-10856-4_70"}],"container-title":["Rechnergest\u00fctzter Entwurf und Architektur mikroelektronischer Systeme"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-84304-4_3.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,27]],"date-time":"2020-11-27T01:55:14Z","timestamp":1606442114000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-84304-4_3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1990]]},"ISBN":["9783540531630","9783642843044"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-84304-4_3","relation":{},"subject":[],"published":{"date-parts":[[1990]]}}}