{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T09:49:13Z","timestamp":1764841753043,"version":"3.40.4"},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783662444900"},{"type":"electronic","value":"9783662444917"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014]]},"DOI":"10.1007\/978-3-662-44491-7_2","type":"book-chapter","created":{"date-parts":[[2014,7,21]],"date-time":"2014-07-21T01:13:00Z","timestamp":1405905180000},"page":"16-30","source":"Crossref","is-referenced-by-count":1,"title":["ACRP: Application Customized Reconfigurable Pipeline"],"prefix":"10.1007","author":[{"given":"Guanwu","family":"Wang","sequence":"first","affiliation":[]},{"given":"Lei","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Sikun","family":"Li","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"2_CR1","doi-asserted-by":"publisher","first-page":"31","DOI":"10.2197\/ipsjtsldm.4.31","volume":"4","author":"K. Choi","year":"2011","unstructured":"Choi, K.: Coarse Grained Reconfigurable Array: Architecture and Application Mapping. IPSJ Transactions on System LSI Design Methodology\u00a04, 31\u201346 (2011)","journal-title":"IPSJ Transactions on System LSI Design Methodology"},{"issue":"2","key":"2_CR2","doi-asserted-by":"publisher","first-page":"171","DOI":"10.1145\/508352.508353","volume":"34","author":"K. Compton","year":"2002","unstructured":"Compton, K., Hauck, S.: Reconfigurable Computing: a Survey of System and Software. ACM Computing Surveys\u00a034(2), 171\u2013210 (2002)","journal-title":"ACM Computing Surveys"},{"key":"2_CR3","doi-asserted-by":"crossref","unstructured":"Coldstein, S.C., Schmit, H., Moe, M., Budiu, M., Cadambi, S., Taylor, R.R., Laufer, R.: PipeRench: A Coprocessor for Streaming Multimedia Acceleration. In: ISCA (1999)","DOI":"10.1145\/307338.300982"},{"key":"2_CR4","doi-asserted-by":"crossref","unstructured":"Ebeling, C., Cronquist, D.C., Franklin, P., Secosky, J., Berg, S.G.: Mapping applications to the RaPiD configurable architecture. In: Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, April 16-18, p. 106 (1997)","DOI":"10.1109\/FPGA.1997.624610"},{"key":"2_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"61","DOI":"10.1007\/978-3-540-45234-8_7","volume-title":"Field Programmable Logic and Application","author":"B. Mei","year":"2003","unstructured":"Mei, B., Vernalde, S., Verkest, D., DeMan, H., Lauwereins, R.: ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. In: Cheung, P.Y.K., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol.\u00a02778, pp. 61\u201370. Springer, Heidelberg (2003)"},{"key":"2_CR6","unstructured":"Mei, B., Vernalde, S., Verkest, D., De Man, H., Lauwereins, R.: DRESC: A Retargetable Compiler for Coarse-Grained Reconfigurable Architectures. In: International Conference on Field Programmable Technology, pp. 166\u2013173 (2002)"},{"issue":"2","key":"2_CR7","doi-asserted-by":"publisher","first-page":"127","DOI":"10.1007\/s11227-006-0016-1","volume":"40","author":"G. Dimitroulakos","year":"2007","unstructured":"Dimitroulakos, G., Galanis, M.D., Goutis, C.E.: Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture. J. Supercomput.\u00a040(2), 127\u2013157 (2007)","journal-title":"J. Supercomput."},{"key":"2_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"40","DOI":"10.1007\/978-3-642-28365-9_4","volume-title":"Reconfigurable Computing: Architectures, Tools and Applications","author":"Y. Kim","year":"2012","unstructured":"Kim, Y., Lee, J., Lee, J., Mai, T.X., Heo, I., Paek, Y.: Exploiting both pipeling and data parallelism with SIMD reconfigurable architecture. In: Choy, O.C.S., Cheung, R.C.C., Athanas, P., Sano, K. (eds.) ARC 2012. LNCS, vol.\u00a07199, pp. 40\u201352. Springer, Heidelberg (2012)"},{"key":"2_CR9","unstructured":"Ahn, M., Yoon, J.W., Paek, Y., Kim, Y., Kiemb, M., Choi, K.: A spatical mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. In: Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, March 06-10 (2006)"},{"key":"2_CR10","doi-asserted-by":"crossref","unstructured":"Park, H., Fan, K., Mahlke, S.A., Oh, T., Kim, H., Kim, H.-S.: Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, Canada, October 25-29 (2008)","DOI":"10.1145\/1454115.1454140"},{"key":"2_CR11","unstructured":"Rau, B.R.: Iterative modulo scheduling. Technical report, Hewlett-Packard Lab: HPL-94-115 (1995)"},{"key":"2_CR12","doi-asserted-by":"crossref","unstructured":"Yang, Z., Yan, M., Wang, D., Li, S.: Data Parallelism Optimization for CGRA Loop Pipelining Mapping. Chinese Journal of Computers 36(6) (2012) (in Chinese)","DOI":"10.3724\/SP.J.1016.2013.01280"},{"key":"2_CR13","series-title":"AISC","first-page":"801","volume-title":"Proceedings of the Eighth International Conference on Bio-Inspired Computing: Theories and Application, BIC-TA","author":"L. Zhou","year":"2013","unstructured":"Zhou, L., Liu, D., Tang, M., Liu, H.: Mapping Loops onto Coarse-Grained Reconfigurable Array Using Genetic Algorithm. In: Yin, Z., Pan, L., Fang, X. (eds.) Proceedings of the Eighth International Conference on Bio-Inspired Computing: Theories and Application, BIC-TA. AISC, vol.\u00a0212, pp. 801\u2013808. Springer, Heidelberg (2013)"},{"key":"2_CR14","series-title":"CCIS","doi-asserted-by":"publisher","first-page":"218","DOI":"10.1007\/978-3-642-41635-4_23","volume-title":"Computer Engineering and Technology","author":"L. Zhou","year":"2013","unstructured":"Zhou, L., Liu, H., Liu, D.: A Novel CGRA Architecture and mapping algorithm for application acceleration. In: Xu, W., Xiao, L., Zhang, C., Li, J., Yu, L. (eds.) NCCET 2013. CCIS, vol.\u00a0396, pp. 218\u2013227. Springer, Heidelberg (2013)"},{"key":"2_CR15","unstructured":"Synopsys Corp., http:\/\/www.synopsys.com (accessed January 10, 2014)"},{"key":"2_CR16","unstructured":"SMIC Corp., http:\/\/www.smics.com\/ (accessed January 10, 2014)"},{"key":"2_CR17","unstructured":"Model Technology Corp., http:\/\/www.model.com (accessed January 10, 2014)"},{"key":"2_CR18","unstructured":"Livermore bench, http:\/\/www.netlib.org\/benchmmark\/livermorec (accessed January 10, 2014)"},{"key":"2_CR19","unstructured":"DSPstone, http:\/\/www.ert.rwth-aachen.de\/Projekte\/Tools\/DSPSTONE (accessed January 10, 2014)"},{"key":"2_CR20","unstructured":"MiBench Version1.0, http:\/\/www.eecs.umich.edu\/mibench (accessed January 10, 2014)"}],"container-title":["Communications in Computer and Information Science","Advanced Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-662-44491-7_2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,3]],"date-time":"2025-05-03T21:50:54Z","timestamp":1746309054000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-662-44491-7_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014]]},"ISBN":["9783662444900","9783662444917"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-662-44491-7_2","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2014]]}}}