{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T17:35:13Z","timestamp":1743096913664,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":37,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783662466629"},{"type":"electronic","value":"9783662466636"}],"license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-3-662-46663-6_8","type":"book-chapter","created":{"date-parts":[[2015,4,1]],"date-time":"2015-04-01T14:37:47Z","timestamp":1427899067000},"page":"151-170","source":"Crossref","is-referenced-by-count":2,"title":["Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes"],"prefix":"10.1007","author":[{"given":"Alain","family":"Darte","sequence":"first","affiliation":[]},{"given":"Alexandre","family":"Isoard","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"8_CR1","doi-asserted-by":"crossref","unstructured":"Alias, C., Baray, F., Darte, A.: Bee+Cl@k: An implementation of lattice-based array contraction in the source-to-source translator Rose. In: Int. Conf. on Languages, Compilers, and Tools for Embedded Systems (LCTES 2007), San Diego (2007)","DOI":"10.1145\/1254766.1254778"},{"key":"8_CR2","doi-asserted-by":"crossref","unstructured":"Alias, C., Darte, A., Plesco, A.: Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators. An experience with the Altera C2H HLS tool. In: Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP 2010), pp. 329\u2013332. IEEE Computer Society, Rennes (2010)","DOI":"10.1109\/ASAP.2010.5540967"},{"key":"8_CR3","unstructured":"Alias, C., Darte, A., Plesco, A.: Kernel offloading with optimized remote accesses. Tech. Rep. RR-7697, Inria (July 2011)"},{"key":"8_CR4","doi-asserted-by":"crossref","unstructured":"Alias, C., Darte, A., Plesco, A.: Optimizing remote accesses for offloaded kernels: Application to HLS for FPGA. In: Design, Automation and Test in Europe (DATE 2013), Grenoble, pp. 575\u2013580 (2013)","DOI":"10.7873\/DATE.2013.127"},{"key":"8_CR5","doi-asserted-by":"crossref","unstructured":"Baskaran, M.M., Bondhugula, U., Krishnamoorthy, S., Ramanujam, J., Rountev, A., Sadayappan, P.: Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories. In: 13th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming (PPoPP 2008), pp. 1\u201310 (2008)","DOI":"10.1145\/1345206.1345210"},{"key":"8_CR6","doi-asserted-by":"crossref","unstructured":"Baskaran, M.M., Vasilache, N., Meister, B., Lethin, R.: Automatic communication optimizations through memory reuse strategies. In: 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2012), New Orleans, pp. 277\u2013278 (2012)","DOI":"10.1145\/2145816.2145852"},{"key":"8_CR7","doi-asserted-by":"crossref","unstructured":"Bondhugula, U., Hartono, A., Ramanujam, J., Sadayappan, P.: A practical automatic polyhedral parallelizer and locality optimizer. In: ACM Int. Conf. on Programming Languages Design and Implementation (PLDI 2008), pp. 101\u2013113 (2008)","DOI":"10.1145\/1375581.1375595"},{"key":"8_CR8","doi-asserted-by":"crossref","unstructured":"Boppu, S., Hannig, F., Teich, J.: Loop program mapping and compact code generation for programmable hardware accelerators. In: IEEE Int. Conf. on Application-Specific Systems, Architectures and Processors (ASAP 2013), pp. 10\u201317 (June 2013)","DOI":"10.1109\/ASAP.2013.6567544"},{"issue":"4","key":"8_CR9","doi-asserted-by":"publisher","first-page":"583","DOI":"10.1007\/s10766-013-0261-x","volume":"42","author":"M. Bourgoin","year":"2014","unstructured":"Bourgoin, M., Chailloux, E., Lamotte, J.L.: Efficient abstractions for GPGPU programming. International Journal of Parallel Programming\u00a042(4), 583\u2013600 (2014)","journal-title":"International Journal of Parallel Programming"},{"key":"8_CR10","doi-asserted-by":"crossref","unstructured":"Creusillet, B., Irigoin, F.: Interprocedural array region analyses. In: Int. Workshop on Languages and Compilers for Parallel Computing (LCPC 1996). LNCS, vol. 1033, pp. 46\u201360. Springer (1996)","DOI":"10.1007\/BFb0014191"},{"key":"8_CR11","doi-asserted-by":"crossref","unstructured":"Darte, A., Isoard, A.: Exact and approximated data-reuse optimizations for tiling with parametric sizes. Tech. Rep. RR-8671, Inria (January 2015), \n                      \n                        http:\/\/hal.inria.fr\/hal-01103460","DOI":"10.1007\/978-3-662-46663-6_8"},{"issue":"10","key":"8_CR12","doi-asserted-by":"publisher","first-page":"1242","DOI":"10.1109\/TC.2005.167","volume":"54","author":"A. Darte","year":"2005","unstructured":"Darte, A., Schreiber, R., Villard, G.: Lattice-based memory allocation. IEEE Transactions on Computers\u00a054(10), 1242\u20131257 (2005)","journal-title":"IEEE Transactions on Computers"},{"key":"8_CR13","doi-asserted-by":"crossref","unstructured":"Feautrier, P.: Parametric integer programming. RAIRO Recherche Op\u00e9rationnelle 22(3), 243\u2013268 (1988), corresponding software tool PIP: \n                      \n                        http:\/\/www.piplib.org\/","DOI":"10.1051\/ro\/1988220302431"},{"key":"8_CR14","unstructured":"Feautrier, P., Lengauer, C.: The polyhedron model. In: Padua, D. (ed.) Encyclopedia of Parallel Programming. Springer (2011)"},{"issue":"10","key":"8_CR15","first-page":"1021","volume":"14","author":"G.I. Goumas","year":"2003","unstructured":"Goumas, G.I., Athanasaki, M., Koziris, N.: An efficient code generation technique for tiled iteration spaces. IEEE TPDS\u00a014(10), 1021\u20131034 (2003)","journal-title":"IEEE TPDS"},{"key":"8_CR16","doi-asserted-by":"crossref","unstructured":"Gr\u00f6\u00dflinger, A.: Precise management of scratchpad memories for localising array accesses in scientific codes. In: Compiler Construction (CC 2009), pp. 236\u2013250 (2009)","DOI":"10.1007\/978-3-642-00722-4_17"},{"key":"8_CR17","doi-asserted-by":"crossref","unstructured":"Guelton, S., Amini, M., Creusillet, B.: Beyond do loops: Data transfer generation with convex array regions. In: Int. Workshop on Languages and Compilers for Parallel Computing (LCPC 2013). LNCS, vol. 7760, pp. 249\u2013263. Springer (2013)","DOI":"10.1007\/978-3-642-37658-0_17"},{"key":"8_CR18","unstructured":"Guelton, S., Keryell, R., Irigoin, F.: Compilation pour cible h\u00e9t\u00e9rog\u00e8nes: automatisation des analyses, transformations et d\u00e9cisions n\u00e9cessaires. In: 20\u00e8me Rencontres Fran\u00e7aises du Parall\u00e9lisme (Renpar 2011), Saint Malo, France (May 2011)"},{"key":"8_CR19","doi-asserted-by":"crossref","unstructured":"Hartono, A., Baskaran, M.M., Ramanujam, J., Sadayappan, P.: DynTile: Parametric tiled loop generation for parallel execution on multicore processors. In: Int. Symp. on Parallel and Distributed Processing (IPDPS 2010), pp. 1\u201312 (2010)","DOI":"10.1109\/IPDPS.2010.5470459"},{"key":"8_CR20","doi-asserted-by":"crossref","unstructured":"Irigoin, F., Triolet, R.: Supernode partitioning. In: 15th Symposium on Principles of Programming Languages (POPL 1988), pp. 319\u2013329. ACM, San Diego (1988)","DOI":"10.1145\/73560.73588"},{"key":"8_CR21","doi-asserted-by":"crossref","unstructured":"Issenin, I., Borckmeyer, E., Miranda, M., Dutt, N.: DRDU: A data reuse analysis technique for efficient scratch-pad memory management. ACM Trans. on Design Automation of Electronics Systems (ACM TODAES) 12(2), article 15 (April 2007)","DOI":"10.1145\/1230800.1230807"},{"key":"8_CR22","doi-asserted-by":"crossref","unstructured":"Kandemir, M., Kadayif, I., Choudhary, A., Ramanujam, J., Kolcu, I.: Compiler-directed scratch pad memory optimization for embedded multiprocessors. IEEE Transactions on VLSI Systems 12(3), 281\u2013287 (2004)","DOI":"10.1109\/TVLSI.2004.824299"},{"key":"8_CR23","doi-asserted-by":"crossref","unstructured":"Kim, J., Kim, H., Lee, J.H., Lee, J.: Achieving a single compute device image in OpenCL for multiple GPUs. In: 16th ACM Symposium on Principles and Practice of Parallel Programming (PPoPP 2011), pp. 277\u2013288. ACM (2011)","DOI":"10.1145\/1941553.1941591"},{"key":"8_CR24","doi-asserted-by":"crossref","unstructured":"Lee, S., Eigenmann, R.: OpenMPC: Extended OpenMP programming and tuning for GPUs. In: ACM\/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (SC 2010), pp. 1\u201311 (2010)","DOI":"10.1109\/SC.2010.36"},{"key":"8_CR25","doi-asserted-by":"publisher","first-page":"649","DOI":"10.1016\/S0167-8191(98)00029-5","volume":"24","author":"V. Lefebvre","year":"1998","unstructured":"Lefebvre, V., Feautrier, P.: Automatic storage management for parallel programs. Parallel Computing\u00a024, 649\u2013671 (1998)","journal-title":"Parallel Computing"},{"key":"8_CR26","doi-asserted-by":"crossref","unstructured":"Pai, S., Govindarajan, R., Thazhuthaveetil, M.J.: Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme. In: 21st International Conference on Parallel Architectures and Compilation Techniques (PACT 2012), pp. 33\u201342 (2012)","DOI":"10.1145\/2370816.2370824"},{"key":"8_CR27","unstructured":"PLUTO: An automatic polyhedral parallelizer and locality optimizer for multicores, \n                      \n                        http:\/\/pluto-compiler.sourceforge.net"},{"key":"8_CR28","doi-asserted-by":"crossref","unstructured":"Pouchet, L.N., Zhang, P., Sadayappan, P., Cong, J.: Polyhedral-based data reuse optimization for configurable computing. In: ACM\/SIGDA Int. Symp. on Field Programmable Gate Arrays (FPGA 2013), pp. 29\u201338. ACM (2013)","DOI":"10.1145\/2435264.2435273"},{"key":"8_CR29","unstructured":"Pouchet, L.N.: PolyBench\/C, the polyhedral benchmark suite, \n                      \n                        http:\/\/sourceforge.net\/projects\/polybench\/"},{"key":"8_CR30","doi-asserted-by":"crossref","unstructured":"Renganarayanan, L., Kim, D., Rajopadhye, S.V., Strout, M.M.: Parameterized tiled loops for free. In: Conf. on Programming Language Design and Implementation (PLDI 2007), San Diego, pp. 405\u2013414 (June 2007)","DOI":"10.1145\/1250734.1250780"},{"key":"8_CR31","doi-asserted-by":"crossref","unstructured":"Upadrasta, R., Cohen, A.: Sub-polyhedral scheduling using (unit-)two-variable-per-inequality polyhedra. In: Symp. on Principles of Programming Languages (POPL 2013), Roma, pp. 483\u2013496 (January 2013)","DOI":"10.1145\/2480359.2429127"},{"key":"8_CR32","doi-asserted-by":"crossref","unstructured":"Verdoolaege, S.: isl: An integer set library for the polyhedral model. In: Mathematical Software - ICMS 2010. LNCS, vol. 6327, pp. 299\u2013302. Springer (2010), \n                      \n                        http:\/\/freecode.com\/projects\/isl\/","DOI":"10.1007\/978-3-642-15582-6_49"},{"key":"8_CR33","unstructured":"Verdoolaege, S.: Counting affine calculator and applications. In: 1st Int. Workshop on Polyhedral Compilation Techniques (IMPACT 2011), Chamonix (April 2011)"},{"issue":"4","key":"8_CR34","first-page":"54","volume":"9","author":"S. Verdoolaege","year":"2013","unstructured":"Verdoolaege, S., Juega, J.C., Cohen, A., G\u00f3mez, J.I., Tenllado, C., Catthoor, F.: Polyhedral parallel code generation for CUDA. ACM Transactions on Architecture and Code Optimization (TACO)\u00a09(4), 54 (2013)","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"key":"8_CR35","doi-asserted-by":"crossref","unstructured":"Wolf, M., Lam, M.: A data locality optimizing algorithm. In: ACM Conf. on Programming Language Design and Implementation (PLDI 1991), pp. 30\u201344 (1991)","DOI":"10.1145\/113446.113449"},{"issue":"4","key":"8_CR36","doi-asserted-by":"publisher","first-page":"409","DOI":"10.1142\/S0129626497000401","volume":"7","author":"J. Xue","year":"1997","unstructured":"Xue, J.: On tiling as a loop transformation. Par. Proc. Letters\u00a07(4), 409\u2013424 (1997)","journal-title":"Par. Proc. Letters"},{"key":"8_CR37","doi-asserted-by":"crossref","unstructured":"Xue, J.: Loop Tiling for Parallelism. Kluwer Academic Publishers (2000)","DOI":"10.1007\/978-1-4615-4337-4"}],"container-title":["Lecture Notes in Computer Science","Compiler Construction"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-662-46663-6_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,29]],"date-time":"2019-05-29T14:17:51Z","timestamp":1559139471000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-662-46663-6_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"ISBN":["9783662466629","9783662466636"],"references-count":37,"URL":"https:\/\/doi.org\/10.1007\/978-3-662-46663-6_8","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2015]]}}}