{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,28]],"date-time":"2025-03-28T00:11:59Z","timestamp":1743120719544,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":19,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783662474006"},{"type":"electronic","value":"9783662474013"}],"license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-3-662-47401-3_41","type":"book-chapter","created":{"date-parts":[[2015,6,19]],"date-time":"2015-06-19T08:27:04Z","timestamp":1434702424000},"page":"311-321","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Memory Centric Hardware Prefetching in Multi-core Processors"],"prefix":"10.1007","author":[{"given":"Danfeng","family":"Zhu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rui","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhongzhi","family":"Luan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Depei","family":"Qian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Han","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jihong","family":"Cai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2015,6,20]]},"reference":[{"key":"41_CR1","unstructured":"Hinton, G., Sager, D., Upton, M., Boggs, D., Carmean, D., Kyker, A., Roussel, P.: The microarchitecture of the pentium 4 processor. Intel Technol. J. (Q1) (2001)"},{"issue":"4\/5","key":"41_CR2","doi-asserted-by":"publisher","first-page":"505","DOI":"10.1147\/rd.494.0505","volume":"49","author":"B Sinharoy","year":"2005","unstructured":"Sinharoy, B., Kalla, R.N., Tendler, J.M., Eickemeyer, R.J., Joyner, J.B.: POWER5 system microarchitecture. IBM J. Res. Dev. 49(4\/5), 505\u2013521 (2005)","journal-title":"IBM J. Res. Dev."},{"key":"41_CR3","doi-asserted-by":"publisher","first-page":"639","DOI":"10.1147\/rd.516.0639","volume":"51","author":"HQ Le","year":"2007","unstructured":"Le, H.Q., Starke, W.J., Fields, J.S., Connell, F.O., Nguyen, D.Q., Ronchetti, B.J., Sauer, W.M., Schwarz, E.M., Waden, M.T.: IBM power6 microarchitecture. IBM J. Res. Dev. 51, 639\u2013662 (2007)","journal-title":"IBM J. Res. Dev."},{"key":"41_CR4","doi-asserted-by":"crossref","unstructured":"Doweck, J.: Inside Intel Core microarchitecture and smart memory access. White paper, Intel Research Website (2006). http:\/\/download.intel.com\/technology\/architecture\/sma.pdf","DOI":"10.1109\/HOTCHIPS.2006.7477876"},{"issue":"2","key":"41_CR5","doi-asserted-by":"publisher","first-page":"174","DOI":"10.1145\/358923.358939","volume":"32","author":"S VanderWiel","year":"2000","unstructured":"VanderWiel, S., Lilja, D.J.: Data prefetch mechanisms. ACM Comput. Surv. 32(2), 174\u2013199 (2000)","journal-title":"ACM Comput. Surv."},{"issue":"1","key":"41_CR6","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1109\/TC.2007.250620","volume":"56","author":"X Zhuang","year":"2007","unstructured":"Zhuang, X., Lee, H.-H.: Reducing cache pollution via dynamic data prefetch filtering. IEEE Trans. Comput. 56(1), 18\u201331 (2007). (water)","journal-title":"IEEE Trans. Comput."},{"key":"41_CR7","unstructured":"Srinivasan, S.: Prefetching vs. the memory system: optimizations for multicore server platforms. Ph.D. thesis, University of Maryland, Dept. of Electrical & Computer Engineering (2007)"},{"key":"41_CR8","doi-asserted-by":"crossref","unstructured":"Srinath, S., Mutlu, O., Kim, H., Patt, Y.N.: Feedback directed prefetching: improving the performance and bandwidth-efficiency of hardware prefetchers. In: Proceedings of the 13th International Symposium on High-Performance Computer Architecture (HPCA), Phoenix, AZ, pp. 63\u201374, February 2007","DOI":"10.1109\/HPCA.2007.346185"},{"key":"41_CR9","doi-asserted-by":"crossref","unstructured":"Lee, C.J., Mutlu, O., Narasiman, V., Patt, Y.N.: Prefetch-aware DRAM controllers. In: Proceedings of the 41st International Symposium on Microarchitecture (MICRO), Lake Como, Italy, pp. 200\u2013209, November 2008","DOI":"10.1109\/MICRO.2008.4771791"},{"key":"41_CR10","doi-asserted-by":"crossref","unstructured":"Ebrahimi, E., et al.: Coordinated control of multiple prefetchers in multi-core systems. In: MICRO-42 (2009)","DOI":"10.1145\/1669112.1669154"},{"key":"41_CR11","doi-asserted-by":"crossref","unstructured":"Ebrahimi, E., Lee, C.J., Mutlu, O., Patt, Y.N.: Prefetch-aware shared resource management for multi-core systems. In: Proceedings of the 38th International Symposium on Computer Architecture (ISCA), San Jose, CA, June 2011","DOI":"10.1145\/2000064.2000081"},{"key":"41_CR12","doi-asserted-by":"crossref","unstructured":"Mutlu, O., Moscibroda, T.: Parallelism-aware batch scheduling: enhancing both performance and fairness of shared DRAM systems. In: Proceedings of the 35th International Symposium on Computer Architecture (ISCA), Beijing, China, pp. 63\u201374, June 2008","DOI":"10.1145\/1394608.1382128"},{"key":"41_CR13","doi-asserted-by":"crossref","unstructured":"Lee, C.J., Narasiman, V., Mutlu, O., Patt, Y.N.: Improving memory bank-level parallelism in the presence of prefetching. In: Proceedings of the 42nd International Symposium on Microarchitecture (MICRO), New York, NY, pp. 327\u2013336, December 2009","DOI":"10.1145\/1669112.1669155"},{"key":"41_CR14","doi-asserted-by":"crossref","unstructured":"Stuecheli, J., Kaseridis, D., Daly, D., Hunter, H., John, L.K.: The virtual write queue: coordinating DRAM and last-level cache policies. In: The 37th Interenational Symposium on Computer Architecture, June 2010","DOI":"10.1145\/1815961.1815972"},{"key":"41_CR15","unstructured":"Lee, C.J., Narasiman, V., Ebrahimi, E., Mutlu, O., Patt, Y.N.: DRAM-aware last-level cache writeback: reducing write-caused interference in memory systems. HPS Technical report, TR-HPS-2010\u2013002, April 2010"},{"issue":"2","key":"41_CR16","doi-asserted-by":"crossref","first-page":"132","DOI":"10.1080\/02286203.1998.11760369","volume":"19","author":"JP Casmira","year":"1998","unstructured":"Casmira, J.P., Kaeli, D.R.: Modeling cache pollution. Int. J. Model. Simul. 19(2), 132\u2013138 (1998)","journal-title":"Int. J. Model. Simul."},{"key":"41_CR17","unstructured":"Jain, P., Devadas, S., Rudolph, L.: Controlling cache pollution in prefetching with software-assisted cache replacement. Technical report TR-CSG-462, Massachusetts Institute of Technology (2001)"},{"key":"41_CR18","unstructured":"Megiddo, N., Modha, D.: ARC: a self-tuning, low overhead replacement cache. In: Proceedings the 2nd USENIX Conference on File and Storage Technologies, San Francisco, pp. 115\u2013130, 31 March\u20132 April 2003"},{"key":"41_CR19","doi-asserted-by":"crossref","unstructured":"Wu, C.J., Jaleel, A., Martonosi, M., Steely, S.C., Emer Jr., J.: PACMan: prefetch-aware cache management for high performance caching. In: Proceedings of the 44th International Symposium on Microarchitecture (MICRO) (2011)","DOI":"10.1145\/2155620.2155672"}],"container-title":["Communications in Computer and Information Science","Trustworthy Computing and Services"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-662-47401-3_41","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,2,21]],"date-time":"2023-02-21T03:51:26Z","timestamp":1676951486000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-662-47401-3_41"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"ISBN":["9783662474006","9783662474013"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/978-3-662-47401-3_41","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2015]]},"assertion":[{"value":"20 June 2015","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}