{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T12:40:11Z","timestamp":1756384811853},"publisher-location":"Berlin, Heidelberg","reference-count":25,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783662480953"},{"type":"electronic","value":"9783662480960"}],"license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-3-662-48096-0_2","type":"book-chapter","created":{"date-parts":[[2015,7,24]],"date-time":"2015-07-24T06:16:03Z","timestamp":1437718563000},"page":"16-27","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":12,"title":["Runtime-Aware Architectures"],"prefix":"10.1007","author":[{"given":"Marc","family":"Casas","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Miquel","family":"Moreto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lluc","family":"Alvarez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emilio","family":"Castillo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dimitrios","family":"Chasapis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Timothy","family":"Hayes","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luc","family":"Jaulmes","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oscar","family":"Palomar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Osman","family":"Unsal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adrian","family":"Cristal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eduard","family":"Ayguade","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jesus","family":"Labarta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mateo","family":"Valero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2015,7,25]]},"reference":[{"key":"2_CR1","doi-asserted-by":"crossref","unstructured":"Alvarez, L., Vilanova, L., Moreto, M., Casas, M., Gonz\u00e0lez, M., Martorell, X., Navarro, N., Ayguad\u00e9, E., Valero, M.: Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures. In: International Symposium on Computer Architecture (ISCA), pp. 720\u2013732 (2015)","DOI":"10.1145\/2872887.2750411"},{"issue":"3","key":"2_CR2","doi-asserted-by":"publisher","first-page":"404","DOI":"10.1109\/TPDS.2008.105","volume":"20","author":"E Ayguad\u00e9","year":"2009","unstructured":"Ayguad\u00e9, E., Copty, N., Duran, A., Hoeflinger, J., Lin, Y., Massaioli, F., Teruel, X., Unnikrishnan, P., Zhang, G.: The design of OpenMP tasks. IEEE Trans. Parallel Distrib. Syst. 20(3), 404\u2013418 (2009)","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"2_CR3","doi-asserted-by":"crossref","unstructured":"Ayguad\u00e9, E., Duran, A., Hoeflinger, J., Massaioli, F., Teruel, X.: An experimental evaluation of the new OpenMP tasking model. In: LCPC, pp. 63\u201377 (2007)","DOI":"10.1007\/978-3-540-85261-2_5"},{"key":"2_CR4","doi-asserted-by":"crossref","unstructured":"Bellens, P., Perez, J.M., Badia, R.M., Labarta, J.: CellSs: a programming model for the cell B.E. architecture. In: Supercomputing (SC) (2006)","DOI":"10.1109\/SC.2006.17"},{"key":"2_CR5","unstructured":"Bienia, C.: Benchmarking Modern Multiprocessors. Ph.D. thesis, Princeton University, January 2011"},{"key":"2_CR6","doi-asserted-by":"crossref","unstructured":"Carter, N.P., Agrawal, A., Borkar, S., Cledat, R., David, H., Dunning, D., Fryman, J.B., Ganev, I., Golliver, R.A., Knauerhase, R.C., Lethin, R., Meister, B., Mishra, A.K., Pinfold, W.R., Teller, J., Torrellas, J., Vasilache, N., Venkatesh, G., Xu, J.: Runnemede: An architecture for ubiquitous high-performance computing. In: International Symposium on High Performance Computer Architecture (HPCA), pp. 198\u2013209 (2013)","DOI":"10.1109\/HPCA.2013.6522319"},{"key":"2_CR7","doi-asserted-by":"crossref","unstructured":"Chapman, B.: The multicore programming challenge. In: International Conference on Advanced Parallel Processing Technologies (APPT), pp. 3\u20133 (2007)","DOI":"10.1007\/978-3-540-76837-1_3"},{"issue":"2","key":"2_CR8","doi-asserted-by":"publisher","first-page":"173","DOI":"10.1142\/S0129626411000151","volume":"21","author":"A Duran","year":"2011","unstructured":"Duran, A., Ayguad\u00e9, E., Badia, R.M., Labarta, J., Martinell, L., Martorell, X., Planas, J.: OmpSs: a proposal for programming heterogeneous multi-core architectures. Parall. Proc. Lett. 21(2), 173\u2013193 (2011)","journal-title":"Parall. Proc. Lett."},{"key":"2_CR9","doi-asserted-by":"crossref","unstructured":"Etsion, Y., Cabarcas, F., Rico, A., Ram\u00edrez, A., Badia, R.M., Ayguad\u00e9, E., Labarta, J., Valero, M.: Task superscalar: An out-of-order task pipeline. In: MICRO, pp. 89\u2013100 (2010)","DOI":"10.1109\/MICRO.2010.13"},{"key":"2_CR10","doi-asserted-by":"crossref","unstructured":"Hayes, T., Palomar, O., Unsal, O.S., Cristal, A., Valero, M.: VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors. In: International Symposium on High Performance Computer Architecture (HPCA), pp. 26\u201338 (2015)","DOI":"10.1109\/HPCA.2015.7056019"},{"key":"2_CR11","volume-title":"Computer Architecture - A Quantitative Approach","author":"JL Hennessy","year":"2012","unstructured":"Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach, 5th edn. Morgan Kaufmann, San Francisco (2012)","edition":"5"},{"key":"2_CR12","unstructured":"International technology roadmap for semiconductors (ITRS) (2011)"},{"issue":"8","key":"2_CR13","doi-asserted-by":"publisher","first-page":"57","DOI":"10.1145\/2038037.1941563","volume":"46","author":"JC Jenista","year":"2011","unstructured":"Jenista, J.C., Eom, Yh, Demsky, B.C.: OoOJava: Software out-of-order execution. SIGPLAN Not. 46(8), 57\u201368 (2011)","journal-title":"SIGPLAN Not."},{"key":"2_CR14","doi-asserted-by":"crossref","unstructured":"Kelm, J.H., Johnson, D.R., Johnson, M.R., Crago, N.C., Tuohy, W., Mahesri, A., Lumetta, S.S., Frank, M.I., Patel, S.J.: Rigel: An architecture and scalable programming interface for a 1000-core accelerator. In: ISCA 09, pp. 140\u2013151","DOI":"10.1145\/1555815.1555774"},{"key":"2_CR15","doi-asserted-by":"crossref","unstructured":"Kumar, S., Hughes, C.J., Nguyen, A.: Carbon: Architectural support for fine-grained parallelism on chip multiprocessors. In: International Symposium on Computer Architecture (ISCA), pp. 162\u2013173 (2007)","DOI":"10.1145\/1273440.1250683"},{"key":"2_CR16","doi-asserted-by":"crossref","unstructured":"Manivannan, M., Stenstrom, P.: Runtime-guided cache coherence optimizations in multi-core architectures. In: International Parallel and Distributed Processing Symposium (IPDPS), pp. 625\u2013636 (2014)","DOI":"10.1109\/IPDPS.2014.71"},{"key":"2_CR17","doi-asserted-by":"crossref","unstructured":"Marjanovi\u0107, V., Labarta, J., Ayguad\u00e9, E., Valero, M.: Overlapping communication and computation by using a hybrid mpi\/smpss approach. In: Proceedings of the 24th ACM International Conference on Supercomputing, ICS 2010, pp. 5\u201316. ACM, New York (2010)","DOI":"10.1145\/1810085.1810091"},{"key":"2_CR18","unstructured":"OpenMP Architecture Review Board: OpenMP application program interface version 4.0, July 2013. \n                      http:\/\/www.openmp.org\/mp-documents\/OpenMP4.0.0.pdf"},{"key":"2_CR19","doi-asserted-by":"crossref","unstructured":"Papaefstathiou, V., Katevenis, M.G., Nikolopoulos, D.S., Pnevmatikatos, D.: Prefetching and cache management using task lifetimes. In: International Conference on Supercomputing (ICS), pp. 325\u2013334 (2013)","DOI":"10.1145\/2464996.2465443"},{"key":"2_CR20","unstructured":"Podobas, A., Brorsson, M.: A comparison of some recent task-based parallel programming models. In: Multiprog (2010)"},{"issue":"5","key":"2_CR21","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1109\/MM.2010.79","volume":"30","author":"A Ram\u00edrez","year":"2010","unstructured":"Ram\u00edrez, A., Cabarcas, F., Juurlink, B.H.H., Alvarez, M., S\u00e1nchez, F., Azevedo, A., Meenderinck, C., Ciobanu, C.B., Isaza, S., Gaydadjiev, G.: The SARC architecture. IEEE Micro 30(5), 16\u201329 (2010)","journal-title":"IEEE Micro"},{"issue":"8","key":"2_CR22","doi-asserted-by":"publisher","first-page":"301","DOI":"10.1145\/2370036.2145864","volume":"47","author":"G Tzenakis","year":"2012","unstructured":"Tzenakis, G., Papatriantafyllou, A., Kesapides, J., Pratikakis, P., Vandierendonck, H., Nikolopoulos, D.S.: BDDT: Block-level dynamic dependence analysis for deterministic task-based parallelism. SIGPLAN Not. 47(8), 301\u2013302 (2012)","journal-title":"SIGPLAN Not."},{"issue":"1","key":"2_CR23","first-page":"29","volume":"1","author":"M Valero","year":"2014","unstructured":"Valero, M., Moreto, M., Casas, M., Ayguade, E., Labarta, J.: Runtime-aware architectures: A first approach. Int. J. Supercomputing Front. Innovations 1(1), 29\u201344 (2014)","journal-title":"Int. J. Supercomputing Front. Innovations"},{"key":"2_CR24","doi-asserted-by":"crossref","unstructured":"Vandierendonck, H., Tzenakis, G., Nikolopoulos, D.: A unified scheduler for recursive and task dataflow parallelism. In: International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 1\u201311, October 2011","DOI":"10.1109\/PACT.2011.7"},{"issue":"1","key":"2_CR25","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1145\/216585.216588","volume":"23","author":"WA Wulf","year":"1995","unstructured":"Wulf, W.A., McKee, S.A.: Hitting the memory wall: Implications of the obvious. SIGARCH Comput. Archit. News 23(1), 20\u201324 (1995)","journal-title":"SIGARCH Comput. Archit. News"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2015: Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-662-48096-0_2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,20]],"date-time":"2020-04-20T00:32:07Z","timestamp":1587342727000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-662-48096-0_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"ISBN":["9783662480953","9783662480960"],"references-count":25,"URL":"https:\/\/doi.org\/10.1007\/978-3-662-48096-0_2","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2015]]},"assertion":[{"value":"25 July 2015","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}