{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T15:27:43Z","timestamp":1742916463489,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783662492826"},{"type":"electronic","value":"9783662492833"}],"license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016]]},"DOI":"10.1007\/978-3-662-49283-3_3","type":"book-chapter","created":{"date-parts":[[2016,1,13]],"date-time":"2016-01-13T20:06:37Z","timestamp":1452715597000},"page":"23-30","source":"Crossref","is-referenced-by-count":0,"title":["Thermal-Aware Floorplanner for Multi-core 3D ICs with Interlayer Cooling"],"prefix":"10.1007","author":[{"given":"Wei","family":"Guo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Minxuan","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peng","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chaoyun","family":"Yao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hongwei","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2016,1,14]]},"reference":[{"key":"3_CR1","unstructured":"International Technology Roadmap for Semiconductors (ITRS) (2013). \n                    http:\/\/www.itrs.net\/Links\/2013ITRS\/Home2013.htm"},{"key":"3_CR2","doi-asserted-by":"crossref","unstructured":"Brunschwiler, T., Paredes, S., Drechsler, U., Michel, B., Cesar, W., Leblebici, Y., Wunderle, B., Reichl, H.: Heat-removal performance scaling of interlayer cooled chip stacks. In: 12th IEEE Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), pp. 1\u201312. IEEE, Barcelona (2010)","DOI":"10.1109\/ITHERM.2010.5501254"},{"issue":"4","key":"3_CR3","doi-asserted-by":"publisher","first-page":"327","DOI":"10.1016\/j.vlsi.2010.06.002","volume":"43","author":"JL Ayala","year":"2010","unstructured":"Ayala, J.L., Sridhar, A., Cuesta, D.: Thermal modeling and analysis of 3D multi-processor chips. Integr. VLSI J. 43(4), 327\u2013341 (2010)","journal-title":"Integr. VLSI J."},{"key":"3_CR4","doi-asserted-by":"crossref","unstructured":"Su, B., Gu, J., Shen, L., Huang, W., Greathouse, J.L., Wang, Z.: PPEP: online performance, power, and energy prediction framework and DVFS space exploration. In: 47th IEEE\/ACM International Symposium on Microarchitecture, pp.445\u2013457. IEEE Computer Society, Washington, DC (2014)","DOI":"10.1109\/MICRO.2014.17"},{"issue":"5","key":"3_CR5","doi-asserted-by":"publisher","first-page":"344","DOI":"10.1016\/j.micpro.2012.02.012","volume":"36","author":"D Cuesta","year":"2012","unstructured":"Cuesta, D., Risco-Martin, J.L., Ayala, J.L.: 3D thermal-aware floorplanner using a MILP approximation. Microprocess. Microsyst. 36(5), 344\u2013354 (2012)","journal-title":"Microprocess. Microsyst."},{"issue":"1","key":"3_CR6","doi-asserted-by":"publisher","first-page":"193","DOI":"10.1007\/s11771-012-0991-8","volume":"19","author":"Q Shuang-xi","year":"2012","unstructured":"Shuang-xi, Q., Zhang, M., Liu, G., Liu, T.: Dynamic thermal management by greedy scheduling algorithm. J. Central South Univ. 19(1), 193\u2013199 (2012)","journal-title":"J. Central South Univ."},{"key":"3_CR7","doi-asserted-by":"crossref","unstructured":"Sridhar, A., Vincenzi, A., Ruggiero, M., Brunschwiler, T., Atienza, D.: 3D-ICE: fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling. In: IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 463\u2013470. IEEE Press, San Jose (2010)","DOI":"10.1109\/ICCAD.2010.5653749"},{"key":"3_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"300","DOI":"10.1007\/11847366_31","volume-title":"High Performance Computing and Communications","author":"J Guo","year":"2006","unstructured":"Guo, J., Dai, K., Wang, Z.: A high performance heterogeneous architecture and its optimization design. In: Gerndt, M., Kranzlm\u00fcller, D. (eds.) HPCC 2006. LNCS, vol. 4208, pp. 300\u2013309. Springer, Heidelberg (2006)"},{"key":"3_CR9","doi-asserted-by":"crossref","unstructured":"Ardestani, E.K., Renau, J.: ESESC: a fast multicore simulator using time-based sampling. In: IEEE\/ACM High Performance Computer Architecture (HPCA), pp. 448\u2013459. IEEE, Shenzhen (2013)","DOI":"10.1109\/HPCA.2013.6522340"}],"container-title":["Communications in Computer and Information Science","Computer Engineering and Technology"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-662-49283-3_3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T06:14:10Z","timestamp":1559369650000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-662-49283-3_3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"ISBN":["9783662492826","9783662492833"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-3-662-49283-3_3","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2016]]}}}