{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,3]],"date-time":"2025-06-03T04:01:27Z","timestamp":1748923287820,"version":"3.41.0"},"publisher-location":"Berlin, Heidelberg","reference-count":25,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783662504116"},{"type":"electronic","value":"9783662504123"}],"license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016]]},"DOI":"10.1007\/978-3-662-50412-3_7","type":"book-chapter","created":{"date-parts":[[2016,4,7]],"date-time":"2016-04-07T11:35:57Z","timestamp":1460028957000},"page":"97-119","source":"Crossref","is-referenced-by-count":8,"title":["A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement"],"prefix":"10.1007","author":[{"given":"Itsuo","family":"Takanami","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tadayoshi","family":"Horita","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masakazu","family":"Akiba","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mina","family":"Terauchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tsuneo","family":"Kanno","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2016,4,8]]},"reference":[{"issue":"4","key":"7_CR1","doi-asserted-by":"publisher","first-page":"501","DOI":"10.1109\/12.21143","volume":"38","author":"SY Kung","year":"1989","unstructured":"Kung, S.Y., Jean, S.N., Chang, C.W.: Fault-tolerant array processors using single-track switches. IEEE Trans. Comput. 38(4), 501\u2013514 (1989)","journal-title":"IEEE Trans. Comput."},{"issue":"7","key":"7_CR2","doi-asserted-by":"publisher","first-page":"609","DOI":"10.1109\/TC.1982.1676058","volume":"c\u201331","author":"TE Mangir","year":"1982","unstructured":"Mangir, T.E., Avizienis, A.: Fault-tolerant design for VLSI: Effect of interconnection requirements on yield improvement of VLSI designs. IEEE Trans. Comput. c\u201331(7), 609\u2013615 (1982)","journal-title":"IEEE Trans. Comput."},{"issue":"5","key":"7_CR3","doi-asserted-by":"publisher","first-page":"448","DOI":"10.1109\/TC.1985.1676584","volume":"C\u201334","author":"T Leighton","year":"1985","unstructured":"Leighton, T., Leiserson, E.: Wafer-scale integration of systolic arrays. IEEE Trans. Comput. C\u201334(5), 448\u2013461 (1985)","journal-title":"IEEE Trans. Comput."},{"issue":"6","key":"7_CR4","doi-asserted-by":"publisher","first-page":"833","DOI":"10.1109\/12.24292","volume":"38","author":"CWH Lam","year":"1989","unstructured":"Lam, C.W.H., Li, H.F., Jakakumar, R.: A study of two approaches for reconfiguring fault-tolerant systolic arrays. IEEE Trans. Comput. 38(6), 833\u2013844 (1989)","journal-title":"IEEE Trans. Comput."},{"issue":"4","key":"7_CR5","doi-asserted-by":"publisher","first-page":"515","DOI":"10.1109\/12.21144","volume":"38","author":"JH Kim","year":"1989","unstructured":"Kim, J.H., Reddy, S.M.: On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement. IEEE Trans. Comput. 38(4), 515\u2013525 (1989)","journal-title":"IEEE Trans. Comput."},{"key":"7_CR6","series-title":"MIT Press series in computer systems","volume-title":"Fault-tolerance through reconfiguration of VLSI and WSI arrays","author":"R Negrini","year":"1989","unstructured":"Negrini, R., Sami, M.G., Stefanelli, R.: Fault-tolerance through reconfiguration of VLSI and WSI arrays. MIT Press series in computer systems. MIT Press, Cambridge (1989)"},{"key":"7_CR7","doi-asserted-by":"publisher","first-page":"73","DOI":"10.1109\/2.56854","volume":"23","author":"I Koren","year":"1990","unstructured":"Koren, I., Singh, A.D.: Fault tolerance in VLSI circuits. IEEE Comput. 23, 73\u201383 (1990)","journal-title":"IEEE Comput."},{"issue":"5","key":"7_CR8","doi-asserted-by":"publisher","first-page":"588","DOI":"10.1109\/12.142685","volume":"41","author":"S Dutt","year":"1992","unstructured":"Dutt, S., Hayers, J.P.: Some practical issues in the design of fault-tolerant multiprocessors. IEEE Trans. Comput. 41(5), 588\u2013598 (1992)","journal-title":"IEEE Trans. Comput."},{"issue":"6","key":"7_CR9","first-page":"988","volume":"E80\u2013A","author":"N Shigei","year":"1997","unstructured":"Shigei, N., Miyajima, H., Murashima, S.: On efficient spare arrangements and an algorithm with relocating spares for reconfiguring processor arrays. IEICE Trans. Fundam. E80\u2013A(6), 988\u2013995 (1997)","journal-title":"IEICE Trans. Fundam."},{"issue":"4","key":"7_CR10","doi-asserted-by":"publisher","first-page":"480","DOI":"10.1109\/12.54841","volume":"39","author":"VP Roychowdhury","year":"1989","unstructured":"Roychowdhury, V.P., Bruck, J., Kailath, T.: Efficient algorithms for reconstruction in VLSI\/WSI array. IEEE Trans. Comput. 39(4), 480\u2013489 (1989)","journal-title":"IEEE Trans. Comput."},{"issue":"2","key":"7_CR11","doi-asserted-by":"publisher","first-page":"78","DOI":"10.1109\/MC.1986.1663151","volume":"19","author":"M Sami","year":"1986","unstructured":"Sami, M., Negrini, R., Stefanelli, R.: Fault tolerance techniues for array structures used in supercomputing. IEEE Comput. 19(2), 78\u201387 (1986)","journal-title":"IEEE Comput."},{"key":"7_CR12","doi-asserted-by":"publisher","first-page":"712","DOI":"10.1109\/PROC.1986.13533","volume":"74","author":"M Sami","year":"1986","unstructured":"Sami, M., Stefanelli, R.: Reconfigurable architectures for VLSI processing arrays. Proc. IEEE 74, 712\u2013722 (1986)","journal-title":"Proc. IEEE"},{"issue":"9","key":"7_CR13","doi-asserted-by":"publisher","first-page":"1255","DOI":"10.1109\/43.240073","volume":"12","author":"P Mazumder","year":"1993","unstructured":"Mazumder, P., Jih, Y.S.: Restructuring of square processor arrays by built-in self-repair circuit. IEEE Trans. Comput. Aided Des. 12(9), 1255\u20131265 (1993)","journal-title":"IEEE Trans. Comput. Aided Des."},{"key":"7_CR14","doi-asserted-by":"crossref","unstructured":"Takanami, I., Kurata, K., Watanabe, T.: A neural algorithm for reconstructing mesh-connected processor arrays using single-track switches. Int. Conf. on WSI, 101\u2013110 (1995)","DOI":"10.1109\/ICWSI.1995.515443"},{"issue":"12","key":"7_CR15","first-page":"1545","volume":"E82\u2013D","author":"T Horita","year":"1999","unstructured":"Horita, T., Takanami, I.: An efficient method for reconfiguring the 1 $$\\frac{1}{2}$$ track-switch mesh array. IEICE Trans. Inf. Syst. E82\u2013D(12), 1545\u20131553 (1999)","journal-title":"IEICE Trans. Inf. Syst."},{"issue":"6","key":"7_CR16","doi-asserted-by":"publisher","first-page":"542","DOI":"10.1109\/12.862214","volume":"49","author":"T Horita","year":"2000","unstructured":"Horita, T., Takanami, I.: Fault tolerant processor arrays based on the 1 $$\\frac{1}{2}$$ -track switches with flexible spare distributions. IEEE Trans. Comput. 49(6), 542\u2013552 (2000)","journal-title":"IEEE Trans. Comput."},{"issue":"8","key":"7_CR17","first-page":"1701","volume":"E83\u2013D","author":"T Horita","year":"2000","unstructured":"Horita, T., Takanami, I.: An FPGA implementation of a self-reconfigurable system for the 1 $$\\frac{1}{2}$$ track-switch 2-D mesh array with PE faults. IEICE Trans. Inf. Syst. E83\u2013D(8), 1701\u20131705 (2000)","journal-title":"IEICE Trans. Inf. Syst."},{"issue":"12","key":"7_CR18","first-page":"1801","volume":"E84\u2013D","author":"T Horita","year":"2001","unstructured":"Horita, T., Takanami, I.: A system for efficiently self-reconstructing 1 $$\\frac{1}{2}$$ -track switch torus arrays. IEICE Trans. Inf. Syst. E84\u2013D(12), 1801\u20131809 (2001)","journal-title":"IEICE Trans. Inf. Syst."},{"issue":"12","key":"7_CR19","first-page":"2743","volume":"E86\u2013D","author":"T Horita","year":"2003","unstructured":"Horita, T., Takanami, I.: An efficiently self-reconstructing array system using E-1 $$\\frac{1}{2}$$ -track switches. IEICE Trans. Inf. Syst. E86\u2013D(12), 2743\u20132752 (2003)","journal-title":"IEICE Trans. Inf. Syst."},{"issue":"3","key":"7_CR20","first-page":"213","volume":"16","author":"SY Lin","year":"2009","unstructured":"Lin, S.Y., Shen, W.C., Hsu, C.C., Wu, A.Y.: Fault-tolerant router with built-in self-test\/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems. Int. J. Electr. Eng. 16(3), 213\u2013222 (2009)","journal-title":"Int. J. Electr. Eng."},{"issue":"2","key":"7_CR21","doi-asserted-by":"publisher","first-page":"207","DOI":"10.1109\/TDSC.2009.53","volume":"8","author":"JH Collet","year":"2011","unstructured":"Collet, J.H., Zajac, P., Psarakis, M., Gizopoulos, D.: Chip self-organization and fault-tolerance in massively defective multicore arrays. IEEE Trans. Dependable Secure Comput. 8(2), 207\u2013217 (2011)","journal-title":"IEEE Trans. Dependable Secure Comput."},{"issue":"10","key":"7_CR22","first-page":"2318","volume":"87","author":"I Takanami","year":"2004","unstructured":"Takanami, I.: Self-reconfiguring of 1 $$\\frac{1}{2}$$ -track-switch mesh arrays with spares on one row and one column by simple built-in circuit. IEICE Trans. Inf. Syst. 87(10), 2318\u20132328 (2004)","journal-title":"IEICE Trans. Inf. Syst."},{"issue":"2","key":"7_CR23","doi-asserted-by":"publisher","first-page":"231","DOI":"10.1109\/12.123400","volume":"41","author":"RG Melhem","year":"1992","unstructured":"Melhem, R.G.: Bi-level reconfigurations of fault tolerant arrays. IEEE Trans. Comput. 41(2), 231\u2013239 (1992)","journal-title":"IEEE Trans. Comput."},{"issue":"3","key":"7_CR24","first-page":"315","volume":"E75\u2013D","author":"K Sugihara","year":"1992","unstructured":"Sugihara, K., Kikuno, T.: Analysis of fault tolerance of reconfigurable arrays using spare processors. IEICE Trans. Inf. Syst. E75\u2013D(3), 315\u2013324 (1992)","journal-title":"IEICE Trans. Inf. Syst."},{"key":"7_CR25","doi-asserted-by":"crossref","unstructured":"Takanami, I., Horita, T.: A built-in circuit for self-repairing mesh-connected processor arrays by direct spare replacement. IEEE Int. Symp. on PRDC, 96\u2013104 (2012)","DOI":"10.1109\/PRDC.2012.11"}],"container-title":["Lecture Notes in Computer Science","Transactions on Computational Science XXVII"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-662-50412-3_7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,2]],"date-time":"2025-06-02T07:16:08Z","timestamp":1748848568000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-662-50412-3_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"ISBN":["9783662504116","9783662504123"],"references-count":25,"URL":"https:\/\/doi.org\/10.1007\/978-3-662-50412-3_7","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2016]]}}}