{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T17:12:37Z","timestamp":1742922757328,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":21,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783662588338"},{"type":"electronic","value":"9783662588345"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-3-662-58834-5_7","type":"book-chapter","created":{"date-parts":[[2019,2,22]],"date-time":"2019-02-22T12:12:05Z","timestamp":1550837525000},"page":"121-139","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1802-7829","authenticated-orcid":false,"given":"Ricardo","family":"Ferreira","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1164-9254","authenticated-orcid":false,"given":"Cristoferson","family":"Bueno","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6372-6891","authenticated-orcid":false,"given":"Marcone","family":"Laure","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6580-1250","authenticated-orcid":false,"given":"Monica","family":"Pereira","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7402-4780","authenticated-orcid":false,"given":"Luigi","family":"Carro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2019,2,23]]},"reference":[{"key":"7_CR1","doi-asserted-by":"publisher","DOI":"10.1002\/9780470429983","volume-title":"Bio-inspired and Nanoscale Integrated Computing","author":"M Eshaghian-Wilner","year":"2009","unstructured":"Eshaghian-Wilner, M.: Bio-inspired and Nanoscale Integrated Computing. Wiley, Hoboken (2009)"},{"issue":"4","key":"7_CR2","doi-asserted-by":"publisher","first-page":"306","DOI":"10.1109\/MDT.2005.94","volume":"22","author":"A DeHon","year":"2005","unstructured":"DeHon, A., Naeimi, H.: Seven strategies for tolerating highly defective fabrication. IEEE Des. Test 22(4), 306\u2013315 (2005)","journal-title":"IEEE Des. Test"},{"key":"7_CR3","unstructured":"Hartenstein, R.: A decade of reconfigurable computing: a visionary retrospective. In: Proceedings of Conference on Design, Automation and Test in Europe, DATE 2001, pp. 642\u2013649. IEEE Press, Piscataway (2001)"},{"issue":"5","key":"7_CR4","doi-asserted-by":"publisher","first-page":"493","DOI":"10.1109\/TVLSI.2007.915439","volume":"16","author":"K Compton","year":"2008","unstructured":"Compton, K., Hauck, S.: Automatic design of reconfigurable domain-specific flexible cores. IEEE Trans. Very Large Scale Integr. Syst. 16(5), 493\u2013503 (2008)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"7_CR5","unstructured":"Schmit, H., Whelihan, D., Moe, M., Levine, B., Taylor, R.: PipeRench: a virtualized programmable datapath (2002)"},{"key":"7_CR6","unstructured":"Tanigawa, K., Zuyama, T., Uchida, T., Hironaka, T.: Exploring compact design on high throughput coarse grained reconfigurable architectures. In: 2008 International Conference on Field Programmable Logic and Applications, Heidelberg, pp. 543\u2013546 (2008)"},{"key":"7_CR7","doi-asserted-by":"crossref","unstructured":"Mei, B., Vernalde, S., Verkest, D., Man, H.D., Lauwereins, R.: Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2003, p. 10296. IEEE Computer Society, Washington (2003)","DOI":"10.1049\/ip-cdt:20030833"},{"key":"7_CR8","doi-asserted-by":"crossref","unstructured":"DeHon, A.: Balancing interconnect and computation in a reconfigurable computing array (or, why you don\u2019t really want 100 In: Proceedings of the 1999 ACM\/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA 1999. ACM, New York (1999)","DOI":"10.1145\/296399.296431"},{"key":"7_CR9","unstructured":"Xilinx: The Programmable Logic Data Book 2003. Xilinx Inc., San Jose (2003)"},{"key":"7_CR10","doi-asserted-by":"crossref","unstructured":"DeHon, A.: Compact, multilayer layout for butterfly fat-tree. In: Proceedings of Twelfth ACM Symposium on Parallel Algorithms and Architectures, SPAA 2000, pp. 206\u2013215. ACM, New York (2000)","DOI":"10.1145\/341800.341824"},{"key":"7_CR11","doi-asserted-by":"crossref","unstructured":"Zied, M., Hayder, M., Emna, A., Habib, M.: Efficient tree topology for FPGA interconnect network. In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI, GLSVLSI 2008, pp. 321\u2013326. ACM, New York (2008)","DOI":"10.1145\/1366110.1366186"},{"key":"7_CR12","unstructured":"Adams, G.B., Agrawal, D.P., Siegel, H.J.: A survey and comparison of fault-tolerant multistage interconnection networks. In: IEEE Interconnection Networks for High-Performance Parallel Computers, pp. 654\u2013667 (1994)"},{"issue":"9","key":"7_CR13","doi-asserted-by":"publisher","first-page":"998","DOI":"10.1109\/12.869334","volume":"49","author":"CC Fan","year":"2000","unstructured":"Fan, C.C., Bruck, J.: Tolerating multiple faults in multistage interconnection networks with minimal extra stages. IEEE Trans. Comput. 49(9), 998\u20131004 (2000)","journal-title":"IEEE Trans. Comput."},{"issue":"6","key":"7_CR14","doi-asserted-by":"publisher","first-page":"802","DOI":"10.1109\/TPDS.2008.130","volume":"20","author":"CG Requena","year":"2009","unstructured":"Requena, C.G., Requena, M.G., Rodr\u00edguez, P.L., Duato, J.F.: FT2EI: a dynamic fault-tolerant routing methodology for fat trees with exclusion intervals. IEEE Trans. Parallel Distrib. Syst. 20(6), 802\u2013817 (2009)","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"7_CR15","doi-asserted-by":"crossref","unstructured":"Ansari, A., Gupta, S., Feng, S., Mahlke, S.: ZerehCache: armoring cache architectures in high defect density technologies. In: Proceedings of the 42nd Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 42, pp. 100\u2013110. ACM, New York (2009)","DOI":"10.1145\/1669112.1669127"},{"issue":"12","key":"7_CR16","doi-asserted-by":"publisher","first-page":"1145","DOI":"10.1109\/T-C.1975.224157","volume":"24","author":"DH Lawrie","year":"1975","unstructured":"Lawrie, D.H.: Access and alignment of data in an array processor. IEEE Trans. Comput. 24(12), 1145\u20131155 (1975)","journal-title":"IEEE Trans. Comput."},{"issue":"11","key":"7_CR17","doi-asserted-by":"publisher","first-page":"1270","DOI":"10.1109\/12.324560","volume":"43","author":"TY Feng","year":"1994","unstructured":"Feng, T.Y., Seo, S.W.: A new routing algorithm for a class of rearrangeable networks. IEEE Trans. Comput. 43(11), 1270\u20131280 (1994)","journal-title":"IEEE Trans. Comput."},{"key":"7_CR18","unstructured":"Kamiura, N., Kodera, T., Matsui, N.: Fault tolerant multistage interconnection networks with widely dispersed paths. In: Asian Test Symposium (2000)"},{"key":"7_CR19","doi-asserted-by":"crossref","unstructured":"Ferreira, R., Laure, M., Beck, A., Lo, T., Rutzig, M., Carro, L.: A low cost and adaptable routing network for reconfigurable systems. In: IEEE Reconfigurable Architecture Workshop RAW (2009)","DOI":"10.1109\/IPDPS.2009.5161217"},{"key":"7_CR20","doi-asserted-by":"crossref","unstructured":"Beck, A.C.S., Rutzig, M.B., Gaydadjiev, G.N., Carro, L.: Transparent reconfigurable acceleration for heterogeneous embedded applications. In: Proceedings of Design, Automation and Test in Europe (DATE 2008) (2008)","DOI":"10.1109\/DATE.2008.4484843"},{"key":"7_CR21","doi-asserted-by":"crossref","unstructured":"Mohan, N., Fung, W., Sachdev, M.: Low power priority encoder and multiple match detection circuit for ternary content addressable memory. In: Advanced International Conference on Telecommunications AICT (2006)","DOI":"10.1109\/SOCC.2006.283892"}],"container-title":["Lecture Notes in Computer Science","Transactions on High-Performance Embedded Architectures and Compilers V"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-662-58834-5_7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,9,12]],"date-time":"2022-09-12T11:22:29Z","timestamp":1662981749000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-662-58834-5_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9783662588338","9783662588345"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/978-3-662-58834-5_7","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"23 February 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}