{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,16]],"date-time":"2025-04-16T04:19:02Z","timestamp":1744777142817},"publisher-location":"Berlin, Heidelberg","reference-count":25,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783662599570"},{"type":"electronic","value":"9783662599587"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-3-662-59958-7_7","type":"book-chapter","created":{"date-parts":[[2019,8,28]],"date-time":"2019-08-28T14:03:30Z","timestamp":1567001010000},"page":"109-135","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A Built-In Circuit for Self-reconfiguring Mesh-Connected Processor Arrays with Spares on Diagonal"],"prefix":"10.1007","author":[{"given":"Itsuo","family":"Takanami","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masaru","family":"Fukushi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2019,8,29]]},"reference":[{"issue":"12","key":"7_CR1","doi-asserted-by":"publisher","first-page":"1955","DOI":"10.1109\/5.192075","volume":"80","author":"LW Schaper","year":"1992","unstructured":"Schaper, L.W.: Design of multichip modules. Proc. IEEE 80(12), 1955\u20131964 (1992)","journal-title":"Proc. IEEE"},{"issue":"8","key":"7_CR2","doi-asserted-by":"publisher","first-page":"15","DOI":"10.1149\/1.2982850","volume":"16","author":"K Okamoto","year":"2008","unstructured":"Okamoto, K.: Importance of wafer bonding for the future hype-miniaturized CMOS devices. ECS Trans. 16(8), 15\u201329 (2008)","journal-title":"ECS Trans."},{"key":"7_CR3","unstructured":"Okamoto, K.: Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th Design Automation Conference, pp. 684\u2013689 (2001)"},{"issue":"4","key":"7_CR4","doi-asserted-by":"publisher","first-page":"501","DOI":"10.1109\/12.21143","volume":"38","author":"SY Kung","year":"1989","unstructured":"Kung, S.Y., Jean, S.N., Chang, C.W.: Fault-tolerant array processors using single-track switches. IEEE Trans. Comput. 38(4), 501\u2013514 (1989)","journal-title":"IEEE Trans. Comput."},{"issue":"7","key":"7_CR5","doi-asserted-by":"publisher","first-page":"609","DOI":"10.1109\/TC.1982.1676058","volume":"C-31","author":"Mangir","year":"1982","unstructured":"Mangir, T.E., Avizienis, A.: Fault-tolerant design for VLSI: effect of interconnection requirements on yield improvement of VLSI designs. IEEE Trans. Comput. c-31(7), 609\u2013615 (1982)","journal-title":"IEEE Transactions on Computers"},{"key":"7_CR6","series-title":"MIT Press Sries in Computer Systems","volume-title":"Fault-Tolerance Through Reconfiguration of VLSI and WSI Arrays","author":"R Negrini","year":"1989","unstructured":"Negrini, R., Sami, M.G., Stefanelli, R.: Fault-Tolerance Through Reconfiguration of VLSI and WSI Arrays. MIT Press Sries in Computer Systems. MIT Press, Cambridge (1989)"},{"issue":"7","key":"7_CR7","doi-asserted-by":"publisher","first-page":"73","DOI":"10.1109\/2.56854","volume":"23","author":"I Koren","year":"1990","unstructured":"Koren, I., Singh, A.D.: Fault tolerance in VLSI circuits. IEEE Comput. 23(7), 73\u201383 (1990)","journal-title":"IEEE Comput."},{"issue":"4","key":"7_CR8","doi-asserted-by":"publisher","first-page":"480","DOI":"10.1109\/12.54841","volume":"39","author":"VP Roychowdhury","year":"1989","unstructured":"Roychowdhury, V.P., Bruck, J., Kailath, T.: Efficient algorithms for reconstruction in VLSI\/WSI array. IEEE Trans. Comput. 39(4), 480\u2013489 (1989)","journal-title":"IEEE Trans. Comput."},{"issue":"11","key":"7_CR9","doi-asserted-by":"publisher","first-page":"1281","DOI":"10.1109\/12.247834","volume":"42","author":"TA Varvarigou","year":"1993","unstructured":"Varvarigou, T.A., Roychowdhury, V.P., Kailath, T.: Reconfiguring processor arrays using multiple-track models: the 3 - tracks - 1 - spare - approach. IEEE Trans. Comput. 42(11), 1281\u20131293 (1993)","journal-title":"IEEE Trans. Comput."},{"key":"7_CR10","unstructured":"Fukushi, M., Fukushima, Y., Horiguchi, S.: A genetic approach for the reconfiguration of degradable processor arrays. In: IEEE 20th International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 63\u201371, October 2005"},{"key":"7_CR11","doi-asserted-by":"crossref","unstructured":"Fukushima, Y., Fukushi, M., Horiguchi, S.: An improved reconfiguration method for degradable processor arrays using genetic algorithm. In: IEEE 21st International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 353\u2013361, October 2006","DOI":"10.1109\/DFT.2006.15"},{"key":"7_CR12","doi-asserted-by":"crossref","unstructured":"Wu, J., Zhu, L., He, P., Jiang, G.: Reconfigurations for processor arrays with faulty switches and links. In: 15th IEEE\/ACM International Symposium on Cluster, Cloud and Grid Computing, pp. 141\u2013148 (2015)","DOI":"10.1109\/CCGrid.2015.47"},{"issue":"12","key":"7_CR13","doi-asserted-by":"publisher","first-page":"3575","DOI":"10.1109\/TPDS.2016.2539958","volume":"27","author":"J Qian","year":"2016","unstructured":"Qian, J., Zhou, Z., Gu, T., Zhao, L., Chang, L.: Optimal reconfiguration of high-performance VLSI subarrays with network flow. IEEE Trans. Parallel Distrib. Syst. 27(12), 3575\u20133587 (2016)","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"issue":"2","key":"7_CR14","doi-asserted-by":"publisher","first-page":"78","DOI":"10.1109\/MC.1986.1663151","volume":"19","author":"R Negrini","year":"1986","unstructured":"Negrini, R., Sami, M., Stefanelli, R.: Fault tolerance techniues for array structures used in supercomputing. IEEE Comput. 19(2), 78\u201387 (1986)","journal-title":"IEEE Comput."},{"key":"7_CR15","doi-asserted-by":"publisher","first-page":"712","DOI":"10.1109\/PROC.1986.13533","volume":"74","author":"M Sami","year":"1986","unstructured":"Sami, M., Stefanelli, R.: Reconfigurable architectures for VLSI processing arrays. Proc. IEEE 74, 712\u2013722 (1986)","journal-title":"Proc. IEEE"},{"key":"7_CR16","unstructured":"Takanami, I., Kurata, K., Watanabe, T.: A neural algorithm for reconstructing mesh-connected processor arrays using single-track switches. In: International Conference on WSI, pp. 101\u2013110, January 1995"},{"key":"7_CR17","unstructured":"Horita, T., Takanami, I.: An efficient method for reconfiguring the 1\n                    \n                      \n                    \n                    $$\\frac{1}{2}$$\n                   track-switch mesh array. IEICE Trans. Inf. Syst. E82-D(12), 1545\u20131553 (1999)"},{"issue":"6","key":"7_CR18","doi-asserted-by":"publisher","first-page":"542","DOI":"10.1109\/12.862214","volume":"49","author":"T Horita","year":"2000","unstructured":"Horita, T., Takanami, I.: Fault tolerant processor arrays based on the 1\n                    \n                      \n                    \n                    $$\\frac{1}{2}$$\n                  -track switches with flexible spare distributions. IEEE Trans. Comput. 49(6), 542\u2013552 (2000)","journal-title":"IEEE Trans. Comput."},{"key":"7_CR19","unstructured":"Horita, T., Takanami, I.: An FPGA implementation of a self-reconfigurable system for the 1\n                    \n                      \n                    \n                    $$\\frac{1}{2}$$\n                   track-switch 2-D mesh array with PE faults. IEICE Trans. Inf. Syst. E83-D(8), 1701\u20131705 (2000)"},{"issue":"3","key":"7_CR20","first-page":"213","volume":"16","author":"SY Lin","year":"2009","unstructured":"Lin, S.Y., Shen, W.C., Hsu, C.C., Wu, A.Y.: Fault-tolerant router with built-in self-test\/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems. Int. J. Electr. Eng. 16(3), 213\u2013222 (2009)","journal-title":"Int. J. Electr. Eng."},{"issue":"2","key":"7_CR21","doi-asserted-by":"publisher","first-page":"207","DOI":"10.1109\/TDSC.2009.53","volume":"8","author":"Jacques Henri Collet","year":"2011","unstructured":"Collet, J.H., Zajac, P., Psarakis, M., Gizopoulos. D.: Chip self-organization and fault-tolerance in massively defective multicore arrays. IEEE Trans. Dependable Secur. Comput. 8(2), 207\u2013217 (2011)","journal-title":"IEEE Transactions on Dependable and Secure Computing"},{"key":"7_CR22","unstructured":"Takanami, I.: Self-reconfiguring of 1\n                    \n                      \n                    \n                    $$\\frac{1}{2}$$\n                  -track-switch mesh arrays with spares on one row and one column by simple built-in circuit. IEICE Trans. Inf. Syst. E87-D(10), 2318\u20132328 (2004)"},{"key":"7_CR23","doi-asserted-by":"crossref","unstructured":"Takanami, I., Horita, T.: A built-in circuit for self-repairing mesh-connected processor arrays by direct spare replacement. In: 2012 IEEE 18th Pacific Rim International Symposium on Dependable Computing, pp. 96\u2013104, November 2012","DOI":"10.1109\/PRDC.2012.11"},{"key":"7_CR24","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"97","DOI":"10.1007\/978-3-662-50412-3_7","volume-title":"Transactions on Computational Science XXVII","author":"I Takanami","year":"2016","unstructured":"Takanami, I., Horita, T., Akiba, M., Terauchi, M., Kanno, T.: A built-in self-repair circuit for restructuring mesh-connected processor arrays by direct spare replacement. In: Gavrilova, M.L., Tan, C.J.K. (eds.) Transactions on Computational Science XXVII. LNCS, vol. 9570, pp. 97\u2013119. Springer, Heidelberg (2016). \n                    https:\/\/doi.org\/10.1007\/978-3-662-50412-3_7"},{"key":"7_CR25","doi-asserted-by":"crossref","unstructured":"Takanami, I., Fukushi, M.: A built-in circuit for self-repairing mesh-connected processor arrays with spares on diagonal. In: Proceedings of 22nd Pacific Rim International Symposium on on Dependable Computing, pp. 110\u2013117, January 2017","DOI":"10.1109\/PRDC.2017.24"}],"container-title":["Lecture Notes in Computer Science","Transactions on Computational Science XXXIV"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-662-59958-7_7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,28]],"date-time":"2019-08-28T14:05:59Z","timestamp":1567001159000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-662-59958-7_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9783662599570","9783662599587"],"references-count":25,"URL":"https:\/\/doi.org\/10.1007\/978-3-662-59958-7_7","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"29 August 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}