{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T11:51:20Z","timestamp":1743076280358,"version":"3.40.3"},"publisher-location":"Dordrecht","reference-count":32,"publisher":"Springer Netherlands","isbn-type":[{"type":"print","value":"9789048134847"},{"type":"electronic","value":"9789048134854"}],"license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-90-481-3485-4_14","type":"book-chapter","created":{"date-parts":[[2010,2,9]],"date-time":"2010-02-09T18:47:34Z","timestamp":1265741254000},"page":"293-314","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems"],"prefix":"10.1007","author":[{"given":"Matthias","family":"Alles","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Timo","family":"Vogt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian","family":"Brehm","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Norbert","family":"Wehn","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2010,2,10]]},"reference":[{"key":"14_CR1","doi-asserted-by":"crossref","unstructured":"Alles, M., Vogt, T., Wehn, N.: FlexiChaP: A reconfigurable ASIP for convolutional, Turbo, and LDPC code decoding. In: Proc. 5th International Symposium on Turbo Codes and Related Topics, Lausanne, Switzerland, pp. 84\u201389 (2008)","DOI":"10.1109\/TURBOCODING.2008.4658677"},{"key":"14_CR2","unstructured":"Alles, M., Lehnigk-Emden, T., Brehm, C., Wehn, N.: A rapid prototyping environment for ASIP validation in wireless systems. In: EDA Workshop 2009, Dresden, Germany (2009)"},{"key":"14_CR3","doi-asserted-by":"crossref","unstructured":"Berrou, C., Glavieux, A., Thitimajshima, P.: Near Shannon limit error-correcting coding and decoding: turbo-codes. In: Proc. 1993 International Conference on Communications (ICC \u201993), Geneva, Switzerland, pp. 1064\u20131070 (1993)","DOI":"10.1109\/ICC.1993.397441"},{"key":"14_CR4","doi-asserted-by":"crossref","unstructured":"Berrou, C., Jezequel, M., Doullard, C., Kerouedan, S.: The advantages of non-binary turbo codes. In: Proceedings of Information Theory Workshop, Cairns, Australia, pp. 61\u201363 (2001)","DOI":"10.1109\/ITW.2001.955136"},{"key":"14_CR5","unstructured":"Boutillon, E., Castura, J., Kschischang, F.: Decoder-first code design. In: Proc. 2nd International Symposium on Turbo Codes & Related Topics, Brest, France, pp. 459\u2013462 (2000)"},{"issue":"8","key":"14_CR6","doi-asserted-by":"publisher","first-page":"1288","DOI":"10.1109\/TCOMM.2005.852852","volume":"53","author":"J. Chen","year":"2005","unstructured":"Chen, J., Dholakia, A., Eleftheriou, E., Fossorier, M.P.C., Hu, X.Y.: Reduced-complexity decoding of LDPC codes. IEEE Trans. Commun. 53(8), 1288\u20131299 (2005)","journal-title":"IEEE Trans. Commun."},{"key":"14_CR7","unstructured":"CoWare, http:\/\/www.coware.com"},{"key":"14_CR8","unstructured":"Dawid, H.: Algorithmen und Schaltungsarchitekturen zur Maximum a Posteriori Faltungsdecodierung. PhD thesis, RWTH Aachen, Shaker Verlag, Aachen, Germany (1996). In German"},{"issue":"1","key":"14_CR9","doi-asserted-by":"publisher","first-page":"21","DOI":"10.1109\/TIT.1962.1057683","volume":"8","author":"R.G. Gallager","year":"1962","unstructured":"Gallager, R.G.: Low-density parity-check codes. IRE Trans. Inf. Theory 8(1), 21\u201328 (1962)","journal-title":"IRE Trans. Inf. Theory"},{"key":"14_CR10","unstructured":"Genode FPGA Graphics (FX), http:\/\/www.genode-labs.com\/products\/fpga-graphics"},{"key":"14_CR11","unstructured":"Gilbert, F.: Optimized, highly parallel architectures for iterative decoding algorithms. PhD thesis, Microelectronic Systems Design Research Group, Department of Electrical Engineering and Information Technology, University of Kaiserslautern (2003). ISBN 3-936890-06-4"},{"key":"14_CR12","doi-asserted-by":"crossref","unstructured":"Glossner, J., Iancu, D., Moudgill, M., Nacer, G., Jinturkar, S., Schulte, M.: The Sandbridge SB3011 SDR platform. In: Joint IST Workshop on Mobile Future and the Symposium on Trends in Communications (SympoTIC \u201906), pp.\u00a0ii\u2013v (2006)","DOI":"10.1109\/TIC.2006.1708006"},{"key":"14_CR13","unstructured":"IMEC: Scientific Report 2006: Software Defined Radio Flexible Air Interface. www.microelektronica.be\/wwwinter\/mediacenter\/en\/SR2006\/681340.html (2006)"},{"key":"14_CR14","doi-asserted-by":"publisher","unstructured":"Ituero, P., Lopez-Vallejo, M.: New schemes in clustered VLIW processors applied to turbo decoding. In: Application-specific Systems, Architectures and Processors, 2006. ASAP \u201906. International Conference on, pp. 291\u2013296 (2006). doi:10.1109\/ASAP.2006.48","DOI":"10.1109\/ASAP.2006.48"},{"key":"14_CR15","doi-asserted-by":"crossref","unstructured":"Krishnaiah, G., Engin, N., Sawitzki, S.: Scalable reconfigurable channel decoder architecture for future wireless handsets. In: Proc. 2007 Design, Automation and Test in Europe (DATE \u201907) (2007)","DOI":"10.1109\/DATE.2007.364524"},{"key":"14_CR16","doi-asserted-by":"crossref","unstructured":"Lin, Y., Lee, H., Woh, M., Harel, Y., Mahlke, S., Mudge, T., Chakrabarti, C., Flautner, K.: SODA: A low-power architecture for software radio. In: Proc. 33rd International Symposium on Computer Architecture (ISCA\u201906), pp. 89\u2013101 (2006)","DOI":"10.1145\/1150019.1136494"},{"issue":"1","key":"14_CR17","doi-asserted-by":"publisher","first-page":"85","DOI":"10.1109\/JSSC.2005.859319","volume":"41","author":"A. Lodi","year":"2006","unstructured":"Lodi, A., Cappelli, A., Bocchi, M., Mucci, C., Innocenti, M., De\u00a0Bartolomeis, C., Ciccarelli, L., Giansante, R., Deledda, A., Campi, F., Toma, M., Guerrieri, R.: XiSystem: a XiRisc-based SoC with reconfigurable IO module. IEEE J.\u00a0Solid-State Circuits 41(1), 85\u201396 (2006). doi:10.1109\/JSSC.2005.859319","journal-title":"IEEE J.\u00a0Solid-State Circuits"},{"issue":"4","key":"14_CR18","doi-asserted-by":"publisher","first-page":"627","DOI":"10.1109\/TVLSI.2003.816136","volume":"11","author":"M.M. Mansour","year":"2003","unstructured":"Mansour, M.M., Shanbhag, N.R.: VLSI architectures for SISO-APP decoders. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(4), 627\u2013650 (2003)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"14_CR19","doi-asserted-by":"publisher","unstructured":"Matu, E., Seidel, H., Limberg, T., Robelly, P., Fettweis, G.: A GFLOPS vector-DSP for broadband wireless applications. In: Conference 2006, IEEE Custom Integrated Circuits, pp. 543\u2013546 (2006). doi:10.1109\/CICC.2006.320923","DOI":"10.1109\/CICC.2006.320923"},{"key":"14_CR20","unstructured":"Michel, H., Worm, A., M\u00fcnch, WehnN.: Hardware\/software trade-offs for advanced 3G channel coding. In: Proc. 2002 Design, Automation and Test in Europe (DATE \u201902), Paris, France (2002)"},{"key":"14_CR21","unstructured":"ML507 Evaluation Platform, http:\/\/www.xilinx.com\/products\/devkits\/HW-V5-ML507-UNI-G.htm"},{"issue":"1","key":"14_CR22","doi-asserted-by":"publisher","first-page":"92","DOI":"10.1109\/TVLSI.2008.2003164","volume":"17","author":"O. Muller","year":"2009","unstructured":"Muller, O., Baghdadi, A., Jezequel, M.: From parallelism levels to a multi-ASIP architecture for turbo decoding. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(1), 92\u2013102 (2009)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"14_CR23","unstructured":"PACT XPP Technologies, www.pactcorp.com"},{"key":"14_CR24","doi-asserted-by":"crossref","unstructured":"Reed, M.C., Pietrobon, S.S.: Turbo-code termination schemes and a novel alternative for short frames. In: Proc. 1996 International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC \u201996), Taipei, Taiwan, vol.\u00a02, pp.\u00a0354\u2013358 (1996)","DOI":"10.1109\/PIMRC.1996.567415"},{"issue":"2","key":"14_CR25","doi-asserted-by":"publisher","first-page":"119","DOI":"10.1002\/ett.4460080202","volume":"8","author":"P. Robertson","year":"1997","unstructured":"Robertson, P., Hoeher, P., Villebrun, E.: Optimal and sub-optimal maximum a posteriori algorithms suitable for turbo decoding. European Transactions on Telecommunications (ETT) 8(2), 119\u2013125 (1997)","journal-title":"European Transactions on Telecommunications (ETT)"},{"key":"14_CR26","unstructured":"Stretch, http:\/\/www.stretchinc.com"},{"key":"14_CR27","doi-asserted-by":"publisher","first-page":"260","DOI":"10.1109\/TIT.1967.1054010","volume":"IT-13","author":"A.J. Viterbi","year":"1967","unstructured":"Viterbi, A.J.: Error bounds for convolutional codes and an asymptotically optimum decoding algorithm. IEEE Trans. Inform. Theory IT-13, 260\u2013269 (1967)","journal-title":"IEEE Trans. Inform. Theory"},{"key":"14_CR28","volume-title":"Principles of Digital Communication and Coding","author":"A.J. Viterbi","year":"1979","unstructured":"Viterbi, A.J., Omura, J.K.: Principles of Digital Communication and Coding. McGraw\u2013Hill, New York (1979)"},{"issue":"10","key":"14_CR29","doi-asserted-by":"publisher","first-page":"1309","DOI":"10.1109\/TVLSI.2008.2002428","volume":"16","author":"T. Vogt","year":"2008","unstructured":"Vogt, T., Wehn, N.: A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment. IEEE Trans. Very Large Scale Integrat. (VLSI) Syst. 16(10), 1309\u20131320 (2008)","journal-title":"IEEE Trans. Very Large Scale Integrat. (VLSI) Syst."},{"key":"14_CR30","unstructured":"Vogt, T., Neeb, C., Wehn, N.: A reconfigurable multi-processor platform for convolutional and turbo decoding. In: Reconfigurable Communication-centric SoCs (ReCoSoC), Montpellier, France (2006)"},{"key":"14_CR31","unstructured":"Xilinx Inc., http:\/\/www.xilinx.com\/ipcenter"},{"key":"14_CR32","unstructured":"Yuan, L., Mahlke, S., Trevor, M., Chaitali, C., Alastair, R., Krisztian, F.: Design and implementation of turbo decoders for software defined radio. In: Proc. IEEE 2006 Workshop on Signal Processing Systems (SiPS) (2006)"}],"container-title":["Dynamically Reconfigurable Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-90-481-3485-4_14","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,18]],"date-time":"2025-02-18T03:43:32Z","timestamp":1739850212000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-90-481-3485-4_14"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9789048134847","9789048134854"],"references-count":32,"URL":"https:\/\/doi.org\/10.1007\/978-90-481-3485-4_14","relation":{},"subject":[],"published":{"date-parts":[[2010]]},"assertion":[{"value":"10 February 2010","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}