{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T18:43:44Z","timestamp":1743101024807,"version":"3.40.3"},"publisher-location":"Dordrecht","reference-count":24,"publisher":"Springer Netherlands","isbn-type":[{"type":"print","value":"9789048134847"},{"type":"electronic","value":"9789048134854"}],"license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-90-481-3485-4_7","type":"book-chapter","created":{"date-parts":[[2010,2,9]],"date-time":"2010-02-09T18:47:34Z","timestamp":1265741254000},"page":"139-158","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":9,"title":["PolyDyn\u2014Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs"],"prefix":"10.1007","author":[{"given":"Andreas","family":"Schallenberg","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wolfgang","family":"Nebel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Herrholz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philipp A.","family":"Hartmann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kim","family":"Gr\u00fcttner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Frank","family":"Oppenheimer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2010,2,10]]},"reference":[{"unstructured":"Amicucci, C., Ferrandi, F., Santambrogio, M., Sciuto, D.: Sycers: a SystemC design exploration framework for soc reconfigurable architecture. In: International Conference on Engineering of Reconfigurable Systems & Algorithm (ERSA), pp.\u00a063\u201369 (2006)","key":"7_CR1"},{"issue":"2","key":"7_CR2","first-page":"55","volume":"3","author":"K. Asano","year":"2008","unstructured":"Asano, K., Kitamichi, J., Kuroda, K.: Dynamic module library for system level modeling and simulation of dynamically reconfigurable systems. J.\u00a0Comput. 3(2), 55\u201362 (2008)","journal-title":"J.\u00a0Comput."},{"doi-asserted-by":"crossref","unstructured":"Bellows, P., Hutchings, B.: JHDL\u2014an HDL for reconfigurable systems. In: Proc. IEEE Symposium on FPGAs for Custom Computing Machines (1998)","key":"7_CR3","DOI":"10.21236\/ADA450477"},{"doi-asserted-by":"crossref","unstructured":"Brito, A.V., Kuhnle, M., H\u00fcbner, M., Becker, J., Melcher, E.U.K.: Modelling and simulation of dynamic and partially reconfigurable systems using SystemC. In: ISVLSI\u00a0\u201907: Proc. of the IEEE Computer Society Annual Symposium on VLSI, pp.\u00a035\u201340 (2007)","key":"7_CR4","DOI":"10.1109\/ISVLSI.2007.69"},{"unstructured":"Brunzema, C., Grabbe, C., Gr\u00fcttner, K., Hartmann, P.A., Herrholz, A., Kleen, H., Oppenheimer, F., Schallenberg, A., Stehno, C., Schubert, T.: Osss 2.0\u2014a library for synthesisable system-level models in SystemC (2007). http:\/\/system-synthesis.org","key":"7_CR5"},{"unstructured":"F\u00e4ltman, I., Hast, M., Lundgren, A., Malki, S., Montnemery, E., R\u00e5ngevall, A., Sandvall, J., Stamenkovic, M.: A hardware implementation of an MP3 decoder. Technical report, LTH Sweden (2003). Digital IC-Project","key":"7_CR6"},{"unstructured":"Fossy synthesiser. http:\/\/www.system-synthesis.org","key":"7_CR7"},{"unstructured":"Grimpe, E., Timmermann, B., Fandrey, T., Biniasch, R., Oppenheimer, F.: SystemC object-oriented extensions and synthesis features. In: Forum on Design Languages FDL \u201902 (2002). http:\/\/odette.offis.de","key":"7_CR8"},{"unstructured":"Hedberg, H., Lenart, T., Svensson, H.: A complete MP3 decoder on a chip. In: Proc. of the IEEE International Conference on Microelectronic Systems Education (MSE\u201905) CCCD, Department of Electroscience, Lund University (2005).","key":"7_CR9"},{"unstructured":"IEEE Standards Association Standards Board: IEEE Std 1666\u20132005 Open SystemC Lang. Reference Manual (2005). http:\/\/www.systemc.org","key":"7_CR10"},{"unstructured":"Kriaa, L., Adriano, S., Vaumorin, E., Nouacer, R., Blanc, F., Pajaniardja, S., Coussy, P., Martin, E., Heller, D., Tabet, F., Fouilliart, A.: SystemC\u2019mantic: A high level modeling and co-design framework for reconfigurable real time systems. In: Forum on Specification and Design Languages (2005)","key":"7_CR11"},{"doi-asserted-by":"crossref","unstructured":"Lee, T., Derbyshire, A., Luk, W., Cheung, P.: High-level language extensions for run-time reconfigurable systems. In: Proc. IEEE International Conference on Field-Programmable Technology (FPT), pp. 144\u2013151 (2003)","key":"7_CR12","DOI":"10.1109\/FPT.2003.1275742"},{"doi-asserted-by":"crossref","unstructured":"Luk, W., McKeever, S.: Pebble: A language for parametrised and reconfigurable hardware design. In: Proc. International Conference on Field Programmable Logic and Applications (FPL), pp. 9\u201318 (1998)","key":"7_CR13","DOI":"10.1007\/BFb0055228"},{"doi-asserted-by":"crossref","unstructured":"McGregor, G., Lysaght, P.: Self controlling dynamic reconfiguration: A case study. In: Proc. International Conference on Field Programmable Logic and Applications (FPL), pp. 144\u2013154 (1999)","key":"7_CR14","DOI":"10.1007\/978-3-540-48302-1_15"},{"unstructured":"Pelkonen, A., Masselos, K., Cup\u00e1k, M.: System-level modeling of dynamically reconfigurable hardware with SystemC. In: Proc. of International Symposium on Parallel and Distributed Processing (Reconfigurable Architectures Workshop), pp.\u00a0174\u2013181 (2003)","key":"7_CR15"},{"issue":"1","key":"7_CR16","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1297666.1297681","volume":"13","author":"A. Raabe","year":"2008","unstructured":"Raabe, A., Hartmann, P.A., Anlauf, J.K.: ReChannel: Describing and simulating reconfigurable hardware in SystemC. ACM Trans. Des. Autom. Electron. Syst. 13(1), 1\u201318 (2008). doi:10.1145\/1297666.1297681","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"unstructured":"Radetzki, M.: Synthesis of digital circuits from object-oriented specifications. PhD thesis, Carl von Ossietzky University Oldenburg, http:\/\/odette.offis.de (2000)","key":"7_CR17"},{"doi-asserted-by":"crossref","unstructured":"Robertson, I., Irvine, J.: A design flow for partially reconfigurable hardware. In: Trans. on Embedded Computing Syst., pp.\u00a0257\u2013283 (2004)","key":"7_CR18","DOI":"10.1145\/993396.993399"},{"doi-asserted-by":"crossref","unstructured":"Schallenberg, A., Oppenheimer, F., Nebel, W.: Designing for dynamic partially reconfigurable FPGAs with SystemC and OSSS. In: Proc. Forum on Design and Specification Languages (FDL), pp. 440\u2013451 (2004)","key":"7_CR19","DOI":"10.1007\/0-387-26151-6_14"},{"doi-asserted-by":"crossref","unstructured":"Schallenberg, A., Oppenheimer, F., Nebel, W.: OSSS+R: modelling and simulating self-reconfigurable systems. In: Proc. International Conference on Field Programmable Logic and Applications (FPL), pp. 177\u2013182 (2006)","key":"7_CR20","DOI":"10.1109\/FPL.2006.311211"},{"doi-asserted-by":"crossref","unstructured":"Schallenberg, A., Herrholz, A., Hartmann, P.A., Oppenheimer, F., Nebel, W.: Osss+r: A\u00a0framework for application level modelling and synthesis of reconfigurable systems. In: Proceedings\u2014Design and Automation Conference in Europe (DATE 2009) (2009)","key":"7_CR21","DOI":"10.1109\/DATE.2009.5090805"},{"doi-asserted-by":"crossref","unstructured":"Semia, L., Sato, K., Micheli, G.D.: Resolution of dynamic memory allocation and pointers for the behavioral synthesis from C. In: Proc. Design Automation and Test in Europe DATE\u201900, pp. 312\u2013319 (2000)","key":"7_CR22","DOI":"10.1145\/343647.343788"},{"doi-asserted-by":"crossref","unstructured":"Tiensyria, K., Qu, Y., Zhang, Y., Cupak, M., Rynders, L., Vanmeerbeeck, G., Masselos, K., Potamianos, K., Pettisalo, M.: SystemC and OCAPI-xl based system-level design for reconfigurable systems-on-chip. In: Forum on Specification and Design Languages, pp.\u00a0428\u2013439 (2004)","key":"7_CR23","DOI":"10.1007\/0-387-26151-6_18"},{"unstructured":"Xilinx, Inc.: Early access partial reconfiguration user guide (UG208). Xilinx, Inc (2006). http:\/\/www.xilinx.com\/","key":"7_CR24"}],"container-title":["Dynamically Reconfigurable Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-90-481-3485-4_7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,18]],"date-time":"2025-02-18T03:42:53Z","timestamp":1739850173000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-90-481-3485-4_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9789048134847","9789048134854"],"references-count":24,"URL":"https:\/\/doi.org\/10.1007\/978-90-481-3485-4_7","relation":{},"subject":[],"published":{"date-parts":[[2010]]},"assertion":[{"value":"10 February 2010","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}