{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T14:07:03Z","timestamp":1743084423949,"version":"3.40.3"},"publisher-location":"Dordrecht","reference-count":10,"publisher":"Springer Netherlands","isbn-type":[{"type":"print","value":"9789048136599"},{"type":"electronic","value":"9789048136605"}],"license":[{"start":{"date-parts":[[2009,12,15]],"date-time":"2009-12-15T00:00:00Z","timestamp":1260835200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2009,12,15]],"date-time":"2009-12-15T00:00:00Z","timestamp":1260835200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-90-481-3660-5_89","type":"book-chapter","created":{"date-parts":[[2010,2,12]],"date-time":"2010-02-12T15:11:46Z","timestamp":1265987506000},"page":"517-525","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Design of RISC Processor Using VHDL and Cadence"],"prefix":"10.1007","author":[{"given":"Saeid","family":"Moslehpour","sequence":"first","affiliation":[]},{"given":"Chandrasekhar","family":"Puliroju","sequence":"additional","affiliation":[]},{"given":"Akram","family":"Abu-aisheh","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2009,12,15]]},"reference":[{"key":"89_CR1","unstructured":"mackido.com \u2013 What is Risc. Retrieved November 2006 http:\/\/www.mackido.com\/Hardware\/WhatIsRISC.html"},{"key":"89_CR2","unstructured":"Risc Architecture. Retrieved: November 2006 http:\/\/www.geocities.com\/SiliconValley\/Chip\/5014\/arch.html"},{"key":"89_CR3","unstructured":"aallison.com \u2013 Brief History of RISC. Retrieved: November 2006 http:\/\/www.aallison.com\/history.htm"},{"key":"89_CR4","unstructured":"VHDL and Verilog. Retrieved November 2006 http:\/\/course.wilkes.edu\/Engineer1\/"},{"key":"89_CR5","unstructured":"IEEE.ORG \u2013 Vhdl Synthesis model. Retrieved November 2006 http:\/\/www.ewh.ieee.org\/soc\/es\/Nov1997\/01\/INDEX.HTM"},{"key":"89_CR6","unstructured":"RCore54 Processor. Retrieved: November 2006 http:\/\/www.ht-lab.com\/freecores\/risc\/risc.html"},{"key":"89_CR7","unstructured":"PSPICE (Copyright \u00a9 1985 - 2004 Cadence Design Systems, Inc) -PSPICE Online Manual Retrieved: September 2006 (As shown in Appendices) (Copyright \u00a9 1985 - 2004 Cadence Design Systems, Inc)"},{"key":"89_CR8","unstructured":"Sreeram Rajagopalan \u2013 Mixed Level and Mixed Signal Simulation using PSpice A\/D and VHDL VHDL2PSPICE Utility. VHDLPSpice_CDNLive_Sreeram.pdf"},{"key":"89_CR9","unstructured":"Chandrasekhar Puliroju \u2013VHDL synthesis models used in this study."},{"key":"89_CR10","unstructured":"Christopher L Spivey , \u201cCreating PSPICE Parts with VHDL Models.\u201d EL 482: Senior Project Report, Fall 2006"}],"container-title":["Advanced Techniques in Computing Sciences and Software Engineering"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-90-481-3660-5_89","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,27]],"date-time":"2023-01-27T21:59:15Z","timestamp":1674856755000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-90-481-3660-5_89"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,12,15]]},"ISBN":["9789048136599","9789048136605"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-90-481-3660-5_89","relation":{},"subject":[],"published":{"date-parts":[[2009,12,15]]},"assertion":[{"value":"15 December 2009","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}