{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,26]],"date-time":"2025-06-26T04:11:11Z","timestamp":1750911071888,"version":"3.41.0"},"publisher-location":"Dordrecht","reference-count":73,"publisher":"Springer Netherlands","isbn-type":[{"type":"print","value":"9789401772662"},{"type":"electronic","value":"9789401772679"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-94-017-7267-9_13","type":"book-chapter","created":{"date-parts":[[2017,9,26]],"date-time":"2017-09-26T13:54:06Z","timestamp":1506434046000},"page":"377-409","source":"Crossref","is-referenced-by-count":0,"title":["Application-Specific Processors"],"prefix":"10.1007","author":[{"given":"Tulika","family":"Mitra","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,9,27]]},"reference":[{"issue":"1","key":"13_CR1","doi-asserted-by":"crossref","first-page":"34","DOI":"10.1109\/TCAD.2012.2214033","volume":"32","author":"J Ahn","year":"2013","unstructured":"Ahn J, Choi K (2013) Isomorphism-aware identification of custom instructions with i\/o serialization. IEEE Trans Comput-Aided Des Integr Circuits Syst 32(1):34\u201346","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"13_CR2","doi-asserted-by":"crossref","unstructured":"Alippi C, Fornaciari W, Pozzi L, Sami M (1999) A dag-based design approach for reconfigurable VLIW processors. In: Proceedings of the conference on design, automation and test in Europe. ACM, p\u00a057","DOI":"10.1145\/307418.307504"},{"key":"13_CR3","doi-asserted-by":"crossref","unstructured":"Amdahl GM (1967) Validity of the single processor approach to achieving large scale computing capabilities. In: Proceedings of the spring joint computer conference, 18\u201320 Apr 1967. ACM, pp\u00a0483\u2013485","DOI":"10.1145\/1465482.1465560"},{"key":"13_CR4","doi-asserted-by":"crossref","unstructured":"Atasu K, Dimond RG, Mencer O, Luk W, \u00d6zturan C, Diindar G (2007) Optimizing instruction-set extensible processors under data bandwidth constraints. In: Design, automation & test in Europe conference & exhibition, DATE\u201907. IEEE, pp\u00a01\u20136","DOI":"10.1109\/DATE.2007.364657"},{"issue":"1","key":"13_CR5","doi-asserted-by":"crossref","first-page":"52","DOI":"10.1109\/TVLSI.2010.2090543","volume":"20","author":"K Atasu","year":"2012","unstructured":"Atasu K, Luk W, Mencer O, \u00d6zturan C, D\u00fcndar G (2012) Fish: fast instruction synthesis for custom processors. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(1):52\u201365","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"13_CR6","doi-asserted-by":"crossref","unstructured":"Atasu K, Mencer O, Luk W, \u00d6zturan C, D\u00fcndar G (2008) Fast custom instruction identification by convex subgraph enumeration. In: International conference on application-specific systems, architectures and processors, ASAP 2008. IEEE, pp\u00a01\u20136","DOI":"10.1109\/ASAP.2008.4580145"},{"issue":"6","key":"13_CR7","doi-asserted-by":"crossref","first-page":"411","DOI":"10.1023\/B:IJPP.0000004508.14594.b9","volume":"31","author":"K Atasu","year":"2003","unstructured":"Atasu K, Pozzi L, Ienne P (2003) Automatic application-specific instruction-set extensions under microarchitectural constraints. Int J Parallel Program 31(6):411\u2013428","journal-title":"Int J Parallel Program"},{"key":"13_CR8","doi-asserted-by":"crossref","unstructured":"Bauer L, Shafique M, Kramer S, Henkel J (2007) Rispp: rotating instruction set processing platform. In: Proceedings of the 44th annual design automation conference. ACM, pp\u00a0791\u2013796","DOI":"10.1145\/1278480.1278678"},{"key":"13_CR9","first-page":"1331","volume-title":"Polynomial-time subgraph enumeration for automated instruction set extension","author":"P Bonzini","year":"2007","unstructured":"Bonzini P, Pozzi L (2007) Polynomial-time subgraph enumeration for automated instruction set extension. In: Proceedings of the conference on design, automation and test in Europe. EDA Consortium, pp\u00a01331\u20131336"},{"key":"13_CR10","doi-asserted-by":"crossref","unstructured":"Bordoloi UD, Huynh HP, Chakraborty S, Mitra T (2009) Evaluating design trade-offs in customizable processors. In: 46th ACM\/IEEE design automation conference, DAC\u201909. IEEE, pp\u00a0244\u2013249","DOI":"10.1145\/1629911.1629978"},{"issue":"5","key":"13_CR11","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1145\/1941487.1941507","volume":"54","author":"S Borkar","year":"2011","unstructured":"Borkar S, Chien AA (2011) The future of microprocessors. Commun ACM 54(5):67\u201377","journal-title":"Commun ACM"},{"key":"13_CR12","doi-asserted-by":"crossref","unstructured":"Chen L, Tarango J, Mitra T, Brisk P (2013) A just-in-time customizable processor. In: 2013 IEEE\/ACM international conference on computer-aided design (ICCAD). IEEE, pp\u00a0524\u2013531","DOI":"10.1109\/ICCAD.2013.6691166"},{"issue":"2","key":"13_CR13","doi-asserted-by":"crossref","first-page":"359","DOI":"10.1109\/TCAD.2006.883915","volume":"26","author":"X Chen","year":"2007","unstructured":"Chen X, Maskell DL, Sun Y (2007) Fast identification of custom instructions for extensible processors. IEEE Trans Comput-Aided Des Integr Circuits Syst 26(2):359\u2013368","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"13_CR14","doi-asserted-by":"crossref","first-page":"31","DOI":"10.2197\/ipsjtsldm.4.31","volume":"4","author":"K Choi","year":"2011","unstructured":"Choi K (2011) Coarse-grained reconfigurable array: architecture and application mapping. IPSJ Trans Syst LSI Des Methodol 4:31\u201346","journal-title":"IPSJ Trans Syst LSI Des Methodol"},{"key":"13_CR15","doi-asserted-by":"crossref","unstructured":"Clark N, Blome J, Chu M, Mahlke S, Biles S, Flautner K (2005) An architecture framework for transparent instruction set customization in embedded processors. In: Proceedings of the 32nd international symposium on computer architecture (ISCA\u201905). IEEE Computer Society, pp\u00a0272\u2013283","DOI":"10.1109\/ISCA.2005.9"},{"key":"13_CR16","doi-asserted-by":"crossref","unstructured":"Clark N, Kudlur M, Park H, Mahlke S, Flautner K (2004) Application-specific processing on a general-purpose core via transparent instruction set customization. In: 37th international symposium on microarchitecture, MICRO-37 2004. IEEE, pp\u00a030\u201340","DOI":"10.1109\/MICRO.2004.5"},{"key":"13_CR17","doi-asserted-by":"crossref","unstructured":"Cong J, Fan Y, Han G, Jagannathan A, Reinman G, Zhang Z (2005) Instruction set extension with shadow registers for configurable processors. In: Proceedings of the 2005 ACM\/SIGDA 13th international symposium on field-programmable gate arrays. ACM, pp\u00a099\u2013106","DOI":"10.1145\/1046192.1046206"},{"key":"13_CR18","doi-asserted-by":"crossref","unstructured":"Cong J, Fan Y, Han G, Zhang Z (2004) Application-specific instruction generation for configurable processor architectures. In: Proceedings of the 2004 ACM\/SIGDA 12th international symposium on field programmable gate arrays. ACM, pp\u00a0183\u2013189","DOI":"10.1145\/968280.968307"},{"issue":"5","key":"13_CR19","doi-asserted-by":"crossref","first-page":"256","DOI":"10.1109\/JSSC.1974.1050511","volume":"9","author":"RH Dennard","year":"1974","unstructured":"Dennard RH, Gaensslen FH, Rideout VL, Bassous E, LeBlanc AR (1974) Design of Ion-implanted MOSFET\u2019s with very small physical dimensions. IEEE J Solid-State Circuits 9(5):256\u2013268","journal-title":"IEEE J Solid-State Circuits"},{"key":"13_CR20","doi-asserted-by":"crossref","unstructured":"Dubach C, Jones T, O\u2019Boyle M (2007) Microarchitectural design space exploration using an architecture-centric approach. In: Proceedings of the 40th annual IEEE\/ACM international symposium on microarchitecture. IEEE Computer Society, pp\u00a0262\u2013271","DOI":"10.1109\/MICRO.2007.12"},{"key":"13_CR21","doi-asserted-by":"crossref","unstructured":"Esmaeilzadeh H, Blem E, St\u00a0Amant R, Sankaralingam K, Burger D (2011) Dark silicon and the end of multicore scaling. In: International symposium on computer architecture\u00a0(ISCA)","DOI":"10.1145\/2000064.2000108"},{"issue":"5","key":"13_CR22","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1109\/MC.2005.160","volume":"38","author":"D Geer","year":"2005","unstructured":"Geer D (2005) Chip makers turn to multicore processors. Computer 38(5):11\u201313","journal-title":"Computer"},{"issue":"3","key":"13_CR23","doi-asserted-by":"crossref","first-page":"483","DOI":"10.1109\/TCAD.2014.2387375","volume":"34","author":"E Giaquinta","year":"2015","unstructured":"Giaquinta E, Mishra A, Pozzi L (2015) Maximum convex subgraphs under i\/o constraint for automatic identification of custom instructions. IEEE Trans Comput-Aided Des Integr Circuits Syst 34(3):483\u2013494","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"issue":"2","key":"13_CR24","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1109\/40.848473","volume":"20","author":"RE Gonzalez","year":"2000","unstructured":"Gonzalez RE (2000) Xtensa: a configurable and extensible processor. IEEE Micro 20(2):60\u201370","journal-title":"IEEE Micro"},{"issue":"5","key":"13_CR25","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/MM.2006.85","volume":"26","author":"RE Gonzalez","year":"2006","unstructured":"Gonzalez RE (2006) A software-configurable processor architecture. IEEE Micro 26(5):42\u201351","journal-title":"IEEE Micro"},{"key":"13_CR26","doi-asserted-by":"crossref","unstructured":"Govindaraju V, Ho CH, Sankaralingam K (2011) Dynamically specialized datapaths for energy efficient computing. In: 2011 IEEE 17th international symposium on high performance computer architecture (HPCA). IEEE, pp\u00a0503\u2013514","DOI":"10.1109\/HPCA.2011.5749755"},{"key":"13_CR27","doi-asserted-by":"crossref","unstructured":"Gupta S, Feng S, Ansari A, Mahlke S, August D (2011) Bundled execution of recurring traces for energy-efficient general purpose processing. In: Proceedings of the 44th annual IEEE\/ACM international symposium on microarchitecture. ACM, pp\u00a012\u201323","DOI":"10.1145\/2155620.2155623"},{"key":"13_CR28","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1016\/j.jda.2012.02.002","volume":"13","author":"G Gutin","year":"2012","unstructured":"Gutin G, Johnstone A, Reddington J, Scott E, Yeo A (2012) An algorithm for finding input\u2013output constrained convex sets in an acyclic digraph. J Discret Algorithms 13:47\u201358","journal-title":"J Discret Algorithms"},{"key":"13_CR29","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1007\/978-1-4020-6488-3_3","volume-title":"Design, automation, and test in Europe","author":"A Halambi","year":"2008","unstructured":"Halambi A, Grun P, Ganesh V, Khare A, Dutt N, Nicolau A (2008) Expression: a language for architecture exploration through compiler\/simulator retargetability. In: Design, automation, and test in Europe. Springer, The Netherlands, pp\u00a031\u201345"},{"key":"13_CR30","doi-asserted-by":"crossref","unstructured":"Hameed R, Qadeer W, Wachs M, Azizi O, Solomatnikov A, Lee BC, Richardson S, Kozyrakis C, Horowitz M (2010) Understanding sources of inefficiency in general-purpose chips. In: ACM SIGARCH computer architecture news, vol\u00a038, no 3. ACM, pp\u00a037\u201347","DOI":"10.1145\/1815961.1815968"},{"key":"13_CR31","first-page":"1472","volume-title":"Instruction-set customization for real-time embedded systems","author":"H Huynh","year":"2007","unstructured":"Huynh H, Mitra T (2007) Instruction-set customization for real-time embedded systems. In: Proceedings of the conference on design, automation and test in Europe. EDA Consortium, pp\u00a01472\u20131477"},{"key":"13_CR32","first-page":"215","volume-title":"International workshop on embedded computer systems","author":"HP Huynh","year":"2009","unstructured":"Huynh HP, Mitra T (2009) Runtime adaptive extensible embedded processors\u2013a survey. In: International workshop on embedded computer systems. Springer, Berlin\/Heidelberg, pp 215\u2013225"},{"key":"13_CR33","doi-asserted-by":"crossref","unstructured":"Huynh HP, Sim JE, Mitra T (2007) An efficient framework for dynamic reconfiguration of instruction-set customization. In: Proceedings of the 2007 international conference on compilers, architecture, and synthesis for embedded systems. ACM, pp 135\u2013144","DOI":"10.1145\/1289881.1289906"},{"key":"13_CR34","unstructured":"Ienne P, Leupers R (2006) Customizable embedded processors: design technologies and applications. Academic Press"},{"key":"13_CR35","doi-asserted-by":"crossref","unstructured":"Jacob JA, Chow P (1999) Memory interfacing and instruction specification for reconfigurable processors. In: Proceedings of the 1999 ACM\/SIGDA seventh international symposium on field programmable gate arrays. ACM, pp\u00a0145\u2013154","DOI":"10.1145\/296399.296446"},{"key":"13_CR36","doi-asserted-by":"crossref","unstructured":"Jayaseelan R, Liu H, Mitra T (2006) Exploiting forwarding to improve data bandwidth of instruction-set extensions. In: Proceedings of the 43rd annual design automation conference. ACM, pp\u00a043\u201348","DOI":"10.1145\/1146909.1146924"},{"issue":"4","key":"13_CR37","doi-asserted-by":"crossref","first-page":"605","DOI":"10.1145\/605440.605446","volume":"7","author":"R Kastner","year":"2002","unstructured":"Kastner R, Kaplan A, Memik SO, Bozorgzadeh E (2002) Instruction generation for hybrid reconfigurable systems. ACM Trans Des Autom Electron Syst (TODAES) 7(4):605\u2013627","journal-title":"ACM Trans Des Autom Electron Syst (TODAES)"},{"issue":"9","key":"13_CR38","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1109\/MC.2002.1033026","volume":"35","author":"V Kathail","year":"2002","unstructured":"Kathail V, Aditya S, Schreiber R, Rau BR, Cronquist DC, Sivaraman\u00a0M (2002) Pico: automatically designing custom computers. Computer 35(9):39\u201347","journal-title":"Computer"},{"key":"13_CR39","unstructured":"Leibson S (2006) Designing SOCs with configured cores: unleashing the tensilica Xtensa and diamond cores. Academic Press"},{"key":"13_CR40","doi-asserted-by":"crossref","unstructured":"Li T, Sun Z, Jigang W, Lu X (2009) Fast enumeration of maximal valid subgraphs for custom-instruction identification. In: Proceedings of the 2009 international conference on compilers, architecture, and synthesis for embedded systems. ACM, pp\u00a029\u201336","DOI":"10.1145\/1629395.1629402"},{"issue":"11","key":"13_CR41","doi-asserted-by":"crossref","first-page":"1876","DOI":"10.1109\/JSSC.2003.818292","volume":"38","author":"A Lodi","year":"2003","unstructured":"Lodi A, Toma M, Campi F, Cappelli A, Canegallo R, Guerrieri R (2003) A VLIW processor with reconfigurable instruction set for embedded applications. IEEE J Solid-State Circuits 38(11):1876\u20131886","journal-title":"IEEE J Solid-State Circuits"},{"key":"13_CR42","doi-asserted-by":"crossref","unstructured":"Lysecky R, Stitt G, Vahid F (2004) Warp processors. In: ACM transactions on design automation of electronic systems (TODAES), vol\u00a011, no 3. ACM, pp\u00a0659\u2013681","DOI":"10.1145\/996566.1142986"},{"key":"13_CR43","unstructured":"Merritt R (2009) ARM CTO: power surge could create \u2018dark silicon\u2019. EE Times, Oct 2009."},{"issue":"3","key":"13_CR44","first-page":"383","volume":"10","author":"T Mitra","year":"2015","unstructured":"Mitra T (2015) Heterogeneous multi-core architectures. Inf Media Technol 10(3):383\u2013394","journal-title":"Inf Media Technol"},{"key":"13_CR45","unstructured":"Mitra T, Yu P (2005) Satisfying real-time constraints with custom instructions. In: Third IEEE\/ACM\/IFIP international conference on hardware\/software codesign and system synthesis, CODES+ ISSS\u201905. IEEE, pp\u00a0166\u2013171"},{"issue":"1","key":"13_CR46","doi-asserted-by":"crossref","first-page":"23","DOI":"10.1007\/BF02760024","volume":"3","author":"JW Moon","year":"1965","unstructured":"Moon JW, Moser L (1965) On cliques in graphs. Israel J Math 3(1):23\u201328","journal-title":"Israel J Math"},{"key":"13_CR47","unstructured":"Moore GE et\u00a0al (1965) Cramming more components onto integrated circuits"},{"key":"13_CR48","first-page":"215","volume-title":"Power: a first class design constraint for future architectures","author":"T Mudge","year":"2000","unstructured":"Mudge T (2000) Power: a first class design constraint for future architectures. In: International conference on high-performance computing. Springer, pp\u00a0215\u2013224"},{"key":"13_CR49","unstructured":"Nios I (2009) Processor reference handbook"},{"key":"13_CR50","doi-asserted-by":"publisher","first-page":"206","DOI":"10.1145\/264107.264201","volume-title":"Proceedings of the 24th annual international symposium on computer architecture (ISCA\u201997)","author":"S Palacharla","year":"1997","unstructured":"Palacharla S, Jouppi NP, Smith JE (1997) Complexity-effective superscalar processors. In: Proceedings of the 24th annual international symposium on computer architecture (ISCA\u201997), Denver. ACM, New York, pp 206\u2013218. doi: 10.1145\/264107.264201"},{"issue":"3","key":"13_CR51","doi-asserted-by":"crossref","first-page":"305","DOI":"10.3233\/EMC-2005-00034","volume":"1","author":"G Palermo","year":"2005","unstructured":"Palermo G, Silvano C, Zaccaria V (2005) Multi-objective design space exploration of embedded systems. J Embed Comput 1(3):305\u2013316","journal-title":"J Embed Comput"},{"key":"13_CR52","unstructured":"Pan Y (2008) Design methodologies for instruction-set extensible processors. Ph.D. thesis, National University of Singapore"},{"key":"13_CR53","doi-asserted-by":"crossref","unstructured":"Patterson D, Hennessy JL (2012) Computer architecture: a quantitative approach. Elsevier","DOI":"10.1145\/2322176.2322187"},{"key":"13_CR54","doi-asserted-by":"crossref","unstructured":"Pothineni N, Kumar A, Paul K (2007) Application specific datapath extension with distributed i\/o functional units. In: Proceedings of the 20th international conference on VLSI design, Bangalore","DOI":"10.1109\/VLSID.2007.40"},{"issue":"7","key":"13_CR55","doi-asserted-by":"crossref","first-page":"1209","DOI":"10.1109\/TCAD.2005.855950","volume":"25","author":"L Pozzi","year":"2006","unstructured":"Pozzi L, Atasu K, Ienne P (2006) Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans Comput-Aided Des Integr Circuits Syst 25(7):1209\u20131229","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"13_CR56","doi-asserted-by":"crossref","unstructured":"Pozzi L, Ienne P (2005) Exploiting pipelining to relax register-file port constraints of instruction-set extensions. In: Proceedings of the 2005 international conference on compilers, architectures and synthesis for embedded systems. ACM, pp\u00a02\u201310","DOI":"10.1145\/1086297.1086300"},{"key":"13_CR57","unstructured":"Razdan R (1994) Prisc: programmable reduced instruction set computers. Ph.D. thesis, Harvard University Cambridge"},{"issue":"12","key":"13_CR58","doi-asserted-by":"crossref","first-page":"2337","DOI":"10.1109\/TVLSI.2011.2173221","volume":"20","author":"J Reddington","year":"2012","unstructured":"Reddington J, Atasu K (2012) Complexity of computing convex subgraphs in custom instruction synthesis. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(12): 2337\u20132341","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"13_CR59","doi-asserted-by":"crossref","unstructured":"Reddington J, Gutin G, Johnstone A, Scott E, Yeo A (2009) Better than optimal: fast identification of custom instruction candidates. In: International conference on computational science and engineering, CSE\u201909. vol\u00a02. IEEE, pp\u00a017\u201324","DOI":"10.1109\/CSE.2009.167"},{"key":"13_CR60","volume-title":"Connecting customized ip to the microblaze soft processor using the fast simplex link (fsl) channel","author":"HP Rosinger","year":"2004","unstructured":"Rosinger HP (2004) Connecting customized ip to the microblaze soft processor using the fast simplex link (fsl) channel. Xilinx Application Note"},{"key":"13_CR61","doi-asserted-by":"crossref","unstructured":"Shafique M, Garg S, Mitra T, Parameswaran S, Henkel J (2014) Dark silicon as a challenge for hardware\/software co-design. In: Conference on hardware\/software codesign and system synthesis\u00a0(CODES)","DOI":"10.1145\/2656075.2661645"},{"issue":"12","key":"13_CR62","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1109\/MC.2015.374","volume":"48","author":"JM Shalf","year":"2015","unstructured":"Shalf JM, Leland R (2015) Computing beyond moore\u2019s law. Computer 48(12):14\u201323","journal-title":"Computer"},{"key":"13_CR63","doi-asserted-by":"crossref","unstructured":"Tan C, Kulkarni A, Venkataramani V, Karunaratne M, Mitra T, Peh\u00a0LS (2016) Locus: low-power customizable many-core architecture for wearables. In: Proceedings of the international conference on compilers, architecture, and synthesis for embedded systems (CASES)","DOI":"10.1145\/2968455.2968506"},{"issue":"11","key":"13_CR64","doi-asserted-by":"crossref","first-page":"1363","DOI":"10.1109\/TC.2004.104","volume":"53","author":"S Vassiliadis","year":"2004","unstructured":"Vassiliadis S, Wong S, Gaydadjiev G, Bertels K, Kuzmanov G, Panainte\u00a0EM (2004) The molen polymorphic processor. IEEE Trans Comput 53(11):1363\u20131375","journal-title":"IEEE Trans Comput"},{"key":"13_CR65","doi-asserted-by":"crossref","unstructured":"Venkatesh G, Sampson J, Goulding-Hotta N, Venkata SK, Taylor MB, Swanson S (2011) Qscores: trading dark silicon for scalable energy efficiency with quasi-specific cores. In: Proceedings of the 44th annual IEEE\/ACM international symposium on microarchitecture. ACM, pp\u00a0163\u2013174","DOI":"10.1145\/2155620.2155640"},{"key":"13_CR66","doi-asserted-by":"crossref","unstructured":"Verma AK, Brisk P, Ienne P (2007) Rethinking custom ise identification: a new processor-agnostic method. In: Proceedings of the 2007 international conference on compilers, architecture, and synthesis for embedded systems. ACM, pp\u00a0125\u2013134","DOI":"10.1145\/1289881.1289905"},{"key":"13_CR67","doi-asserted-by":"publisher","first-page":"176","DOI":"10.1145\/106972.106991","volume-title":"Proceedings of the fourth international conference on architectural support for programming languages and operating systems (ASPLOS IV)","author":"DW Wall","year":"1991","unstructured":"Wall DW (1991) Limits of instruction-level parallelism. In: Proceedings of the fourth international conference on architectural support for programming languages and operating systems (ASPLOS IV), Santa Clara. ACM, New York, pp 176\u2013188. doi: 10.1145\/106972.106991"},{"key":"13_CR68","doi-asserted-by":"crossref","first-page":"99","DOI":"10.1109\/FPGA.1995.477415","volume-title":"IEEE symposium on FPGAs for custom computing machines","author":"MJ Wirthlin","year":"1995","unstructured":"Wirthlin MJ, Hutchings BL (1995) A dynamic instruction set computer. In: IEEE symposium on FPGAs for custom computing machines. Proceedings. IEEE, pp\u00a099\u2013107"},{"issue":"1","key":"13_CR69","doi-asserted-by":"crossref","first-page":"20","DOI":"10.1145\/216585.216588","volume":"23","author":"WA Wulf","year":"1995","unstructured":"Wulf WA, McKee SA (1995) Hitting the memory wall: implications of the obvious. ACM SIGARCH Comput Archit News 23(1):20\u201324","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"13_CR70","doi-asserted-by":"crossref","unstructured":"Ye ZA, Moshovos A, Hauck S, Banerjee P (2000) CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. In: ACM SIGARCH computer architecture news, vol 28, no 2. ACM, pp. 225\u2013235","DOI":"10.1145\/339647.339687"},{"key":"13_CR71","doi-asserted-by":"crossref","unstructured":"Yu P, Mitra T (2004) Characterizing embedded applications for instruction-set extensible processors. In: Proceedings of the 41st annual design automation conference. ACM, pp\u00a0723\u2013728","DOI":"10.1145\/996566.996764"},{"key":"13_CR72","doi-asserted-by":"crossref","unstructured":"Yu P, Mitra T (2004) Scalable custom instructions identification for instruction-set extensible processors. In: Proceedings of the 2004 international conference on compilers, architecture, and synthesis for embedded systems. ACM, pp\u00a069\u201378","DOI":"10.1145\/1023833.1023844"},{"key":"13_CR73","doi-asserted-by":"crossref","unstructured":"Yu P, Mitra T (2007) Disjoint pattern enumeration for custom instructions identification. In: International conference on field programmable logic and applications, FPL 2007. IEEE, pp\u00a0273\u2013278","DOI":"10.1109\/FPL.2007.4380659"}],"container-title":["Handbook of Hardware\/Software Codesign"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-94-017-7267-9_13","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,25]],"date-time":"2025-06-25T22:15:00Z","timestamp":1750889700000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-94-017-7267-9_13"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789401772662","9789401772679"],"references-count":73,"URL":"https:\/\/doi.org\/10.1007\/978-94-017-7267-9_13","relation":{},"subject":[],"published":{"date-parts":[[2017]]}}}