{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T14:28:03Z","timestamp":1742912883790,"version":"3.40.3"},"publisher-location":"Dordrecht","reference-count":40,"publisher":"Springer Netherlands","isbn-type":[{"type":"print","value":"9789401772662"},{"type":"electronic","value":"9789401772679"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-94-017-7267-9_14","type":"book-chapter","created":{"date-parts":[[2017,9,26]],"date-time":"2017-09-26T09:54:06Z","timestamp":1506419646000},"page":"411-441","source":"Crossref","is-referenced-by-count":0,"title":["Memory Architectures"],"prefix":"10.1007","author":[{"given":"Preeti Ranjan","family":"Panda","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,9,27]]},"reference":[{"key":"14_CR1","doi-asserted-by":"crossref","unstructured":"Aa TV, Palkovic M, Hartmann M, Raghavan P, Dejonghe A, der Perre LV (2011) A multi-threaded coarse-grained array processor for wireless baseband. In: IEEE 9th symposium on application specific processors SASP, San Diego, 5\u20136 June 2011, pp\u00a0102\u2013107","DOI":"10.1109\/SASP.2011.5941087"},{"key":"14_CR2","unstructured":"ARM Advanced RISC Machines Ltd (2006) ARM1136JF-S and ARM1136J-S, Technical Reference Manual, r1p3 edn"},{"key":"14_CR3","doi-asserted-by":"crossref","unstructured":"Carter NP, Agrawal A, Borkar S, Cledat R, David H, Dunning D, Fryman JB, Ganev I, Golliver RA, Knauerhase RC, Lethin R, Meister B, Mishra AK, Pinfold WR, Teller J, Torrellas J, Vasilache N, Venkatesh G, Xu J (2013) Runnemede: an architecture for ubiquitous high-performance computing. In: 19th IEEE international symposium on high performance computer architecture HPCA, Shenzhen, 23\u201327 Feb 2013, pp\u00a0198\u2013209","DOI":"10.1109\/HPCA.2013.6522319"},{"key":"14_CR4","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-2849-1","volume-title":"Custom memory management methodology: exploration of memory organisation for embedded multimedia system design","author":"F Catthoor","year":"1998","unstructured":"Catthoor F, Wuytack S, De Greef E, Balasa F, Nachtergaele L, Vandecappelle A (1998) Custom memory management methodology: exploration of memory organisation for embedded multimedia system design. Kluwer Academic Publishers, Norwell, USA"},{"key":"14_CR5","doi-asserted-by":"crossref","unstructured":"Chakraborty P, Panda PR (2012) Integrating software caches with scratch pad memory. In: Proceedings of the 15th international conference on compilers, architecture, and synthesis for embedded systems, pp\u00a0201\u2013210","DOI":"10.1145\/2380403.2380440"},{"key":"14_CR6","doi-asserted-by":"crossref","unstructured":"Chen G, Ozturk O, Kandemir MT, Karak\u00f6y M (2006) Dynamic scratch-pad memory management for irregular array access patterns. In: Proceedings of the conference on design, automation and test in Europe DATE, Munich, 6\u201310 Mar 2006, pp\u00a0931\u2013936","DOI":"10.1109\/DATE.2006.243810"},{"key":"14_CR7","doi-asserted-by":"crossref","unstructured":"Chen T, Lin H, Zhang T (2008) Orchestrating data transfer for the CELL\/BE processor. In: Proceedings of the 22nd annual international conference on supercomputing, ICS \u201908, pp\u00a0289\u2013298","DOI":"10.1145\/1375527.1375570"},{"key":"14_CR8","doi-asserted-by":"crossref","unstructured":"Coleman S, McKinley KS (1995) Tile size selection using cache organization and data layout. In: Proceedings of the ACM SIGPLAN\u201995 conference on programming language design and implementation (PLDI), pp\u00a0279\u2013290","DOI":"10.1145\/207110.207162"},{"key":"14_CR9","doi-asserted-by":"crossref","unstructured":"Francesco P, Marchal P, Atienza D, Benini L, Catthoor F, Mendias, JM (2004) An integrated hardware\/software approach for run-time scratchpad management. In: Proceedings of the 41st annual design automation conference, DAC\u201904, pp\u00a0238\u2013243","DOI":"10.1145\/996566.996634"},{"key":"14_CR10","doi-asserted-by":"crossref","unstructured":"Givargis T (2003) Improved indexing for cache miss reduction in embedded systems. In: Proceedings of the 40th design automation conference, pp\u00a0875\u2013880","DOI":"10.1145\/775832.776052"},{"key":"14_CR11","volume-title":"Memory architecture exploration for programmable embedded systems","author":"P Grun","year":"2003","unstructured":"Grun P, Dutt N, Nicolau A (2003) Memory architecture exploration for programmable embedded systems. Kluwer Academic Publishers, Boston"},{"key":"14_CR12","volume-title":"Computer architecture: a quantitative approach","author":"JL Hennessy","year":"2003","unstructured":"Hennessy JL, Patterson DA (2003) Computer architecture: a quantitative approach, 3rd edn. Morgan Kaufmann Publishers Inc., San Francisco","edition":"3"},{"key":"14_CR13","doi-asserted-by":"crossref","unstructured":"Jain R, Panda PR, Subramoney S (2016) Machine learned machines: adaptive co-optimization of caches, cores, and on-chip network. In: 2016 design, automation & test in Europe, pp\u00a0253\u2013256","DOI":"10.3850\/9783981537079_0083"},{"key":"14_CR14","doi-asserted-by":"publisher","unstructured":"Jog A, Mishra AK, Xu C, Xie Y, Narayanan V, Iyer R, Das CR (2012) Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. In: Design automation conference (DAC), pp\u00a0243\u2013252. doi: 10.1145\/2228360.2228406","DOI":"10.1145\/2228360.2228406"},{"key":"14_CR15","doi-asserted-by":"crossref","unstructured":"Kandemir MT, Ramanujam J, Irwin MJ, Vijaykrishnan N, Kadayif I, Parikh A (2001) Dynamic management of scratch-pad memory space. In: Proceedings of the 38th design automation conference, pp\u00a0690\u2013695","DOI":"10.1145\/378239.379049"},{"issue":"2","key":"14_CR16","doi-asserted-by":"crossref","first-page":"243","DOI":"10.1109\/TCAD.2003.822123","volume":"23","author":"MT Kandemir","year":"2004","unstructured":"Kandemir MT, Ramanujam J, Irwin MJ, Vijaykrishnan N, Kadayif I, Parikh A (2004) A compiler-based approach for dynamically managing scratch-pad memories in embedded systems. IEEE Trans CAD Integr Circuits Syst 23(2):243\u2013260","journal-title":"IEEE Trans CAD Integr Circuits Syst"},{"key":"14_CR17","doi-asserted-by":"crossref","unstructured":"Komalan MP, Tenllado C, Perez JIG, Fern\u00e1ndez FT, Catthoor F (2015) System level exploration of a STT-MRAM based level 1 data-cache. In: Proceedings of the 2015 design, automation & test in Europe conference & exhibition DATE, Grenoble, 9\u201313 Mar 2015, pp\u00a01311\u20131316","DOI":"10.7873\/DATE.2015.0551"},{"key":"14_CR18","first-page":"63","volume-title":"The cache performance and optimizations of blocked algorithms","author":"MS Lam","year":"1991","unstructured":"Lam MS, Rothberg EE, Wolf ME (1991) The cache performance and optimizations of blocked algorithms. In: ASPLOS-IV proceedings - fourth international conference on architectural support for programming languages and operating systems, pp\u00a063\u201374"},{"key":"14_CR19","unstructured":"Li H, Chen Y (2009) An overview of non-volatile memory technology and the implication for tools and architectures. In: Design, automation test in Europe conference exhibition (DATE), pp\u00a0731\u2013736"},{"key":"14_CR20","doi-asserted-by":"crossref","unstructured":"Liu T, Lin H, Chen T, O\u2019Brien JK, Shao L (2009) Dbdb: optimizing DMA transfer for the CELL BE architecture. In: Proceedings of the 23rd international conference on supercomputing, pp\u00a036\u201345","DOI":"10.1145\/1542275.1542286"},{"key":"14_CR21","doi-asserted-by":"publisher","first-page":"289","DOI":"10.1007\/978-1-4419-9551-3_11","volume-title":"Emerging memory technologies","author":"Y Liu","year":"2014","unstructured":"Liu Y, Yang H, Wang Y, Wang C, Sheng X, Li S, Zhang D, Sun Y (2014) Ferroelectric nonvolatile processor design, optimization, and application. In: Xie Y (ed) Emerging memory technologies. Springer, New York, pp\u00a0289\u2013322. doi: 10.1007\/978-1-4419-9551-3_11"},{"key":"14_CR22","volume-title":"The PowerPC architecture: a specification for a new family of RISC processors","author":"C May","year":"1994","unstructured":"May C, Silha E, Simpson R, Warren H (1994) The PowerPC architecture: a specification for a new family of RISC processors, 2 edn. Morgan Kaufmann, San Francisco, USA","edition":"2"},{"key":"14_CR23","unstructured":"Muralimanohar N, Balasubramonian R, Jouppi NP (2009) CACTI6.0: A tool to model large caches. Technical Report HPL-2009-85, HP Laboratories"},{"key":"14_CR24","doi-asserted-by":"crossref","unstructured":"Nalluri R, Garg R, Panda PR (2007) Customization of register file banking architecture for low power. In: 20th international conference on VLSI design, pp\u00a0239\u2013244","DOI":"10.1109\/VLSID.2007.58"},{"key":"14_CR25","volume-title":"Corporation","author":"NVDIA","year":"2009","unstructured":"NVDIA Corporation (2009) NVIDIA\u2019s Next Generation CUDA Compute Architecture: Fermi"},{"issue":"1","key":"14_CR26","doi-asserted-by":"crossref","first-page":"80","DOI":"10.1111\/j.1467-8659.2007.01012.x","volume":"26","author":"JD Owens","year":"2007","unstructured":"Owens JD, Luebke D, Govindaraju N, Harris M, Kr\u00fcger J, Lefohn A, Purcell TJ (2007) A survey of general-purpose computation on graphics hardware. Comput Graphics Forum 26(1):80\u2013113","journal-title":"Comput Graphics Forum"},{"key":"14_CR27","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4419-6388-8","volume-title":"Power-efficient system design","author":"PR Panda","year":"2010","unstructured":"Panda PR, Silpa B, Shrivastava A, Gummidipudi K (2010) Power-efficient system design. Springer, US"},{"issue":"2","key":"14_CR28","doi-asserted-by":"crossref","first-page":"149","DOI":"10.1145\/375977.375978","volume":"6","author":"PR Panda","year":"2001","unstructured":"Panda PR, Catthoor F, Dutt ND, Danckaert K, Brockmeyer E, Kulkarni C, Vandecappelle A, Kjeldsberg PG (2001) Data and memory optimization techniques for embedded systems. ACM Trans Design Autom Electr Syst 6(2):149\u2013206","journal-title":"ACM Trans Design Autom Electr Syst"},{"key":"14_CR29","doi-asserted-by":"crossref","unstructured":"Panda PR, Dutt ND, Nicolau A (1997) Efficient utilization of scratch-pad memory in embedded processor applications. In: European design and test conference, ED&TC \u201997, Paris, 17\u201320 Mar 1997, pp\u00a07\u201311","DOI":"10.1109\/EDTC.1997.582323"},{"issue":"2","key":"14_CR30","doi-asserted-by":"crossref","first-page":"96","DOI":"10.1109\/43.681260","volume":"17","author":"PR Panda","year":"1998","unstructured":"Panda PR, Dutt ND, Nicolau A (1998) Incorporating DRAM access modes into high-level synthesis. IEEE Trans CAD Integr Circuits Syst 17(2):96\u2013109","journal-title":"IEEE Trans CAD Integr Circuits Syst"},{"issue":"1","key":"14_CR31","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/43.739054","volume":"18","author":"PR Panda","year":"1999","unstructured":"Panda PR, Dutt ND, Nicolau A (1999) Local memory exploration and optimization in embedded systems. IEEE Trans CAD Integr Circuits Syst 18(1):3\u201313","journal-title":"IEEE Trans CAD Integr Circuits Syst"},{"key":"14_CR32","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5107-2","volume-title":"Memory issues in embedded systems-on-chip","author":"PR Panda","year":"1999","unstructured":"Panda PR, Dutt ND, Nicolau A (1999) Memory issues in embedded systems-on-chip. Kluwer Academic Publishers, Boston"},{"issue":"2","key":"14_CR33","doi-asserted-by":"crossref","first-page":"142","DOI":"10.1109\/12.752655","volume":"48","author":"PR Panda","year":"1999","unstructured":"Panda PR, Nakamura H, Dutt ND, Nicolau A (1999) Augmenting loop tiling with data alignment for improved cache performance. IEEE Trans Comput 48(2):142\u2013149","journal-title":"IEEE Trans Comput"},{"key":"14_CR34","doi-asserted-by":"crossref","unstructured":"Qureshi MK, Patt YN (2006) Utility-based cache partitioning: a low-overhead, high-performance, runtime mechanism to partition shared caches. In: 39th annual IEEE\/ACM international symposium on microarchitecture, pp\u00a0423\u2013432","DOI":"10.1109\/MICRO.2006.49"},{"key":"14_CR35","doi-asserted-by":"crossref","unstructured":"Ramo EP, Resano J, Mozos D, Catthoor F (2006) A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead. In: 20th international parallel and distributed processing symposium IPDPS","DOI":"10.1109\/IPDPS.2006.1639435"},{"key":"14_CR36","doi-asserted-by":"publisher","unstructured":"Raoux S, Burr G, Breitwisch M, Rettner C, Chen Y, Shelby R, Salinga M, Krebs D, Chen SH, Lung H, Lam C (2008) Phase-change random access memory: a scalable technology. IBM J Res Dev 52(4.5):465\u2013479. doi: 10.1147\/rd.524.0465","DOI":"10.1147\/rd.524.0465"},{"key":"14_CR37","doi-asserted-by":"crossref","unstructured":"Rodr\u00edguez G, Touri\u00f1o J, Kandemir MT (2014) Volatile STT-RAM scratchpad design and data allocation for low energy. ACM Trans Archit Code Optim (TACO) 11(4):38:1\u201338:26","DOI":"10.1145\/2669556"},{"key":"14_CR38","first-page":"409","volume-title":"Assigning program and data objects to scratchpad for energy reduction","author":"S Steinke","year":"2002","unstructured":"Steinke S, Wehmeyer L, Lee B, Marwedel P (2002) Assigning program and data objects to scratchpad for energy reduction. In: Design, automation and test in Europe, pp\u00a0409\u2013415"},{"issue":"4","key":"14_CR39","doi-asserted-by":"crossref","first-page":"529","DOI":"10.1109\/92.736124","volume":"6","author":"S Wuytack","year":"1998","unstructured":"Wuytack S, Diguet JP, Catthoor F, Man HJD (1998) Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings. IEEE Trans Very Larg Scale Integr Syst 6(4):529\u2013537","journal-title":"IEEE Trans Very Larg Scale Integr Syst"},{"issue":"1","key":"14_CR40","doi-asserted-by":"crossref","first-page":"34","DOI":"10.1145\/1061267.1061270","volume":"2","author":"C Zhang","year":"2005","unstructured":"Zhang C, Vahid F, Yang J, Najjar W (2005) A way-halting cache for low-energy high-performance systems. ACM Trans Archit Code Optim 2(1):34\u201354","journal-title":"ACM Trans Archit Code Optim"}],"container-title":["Handbook of Hardware\/Software Codesign"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-94-017-7267-9_14","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,3]],"date-time":"2019-10-03T20:07:59Z","timestamp":1570133279000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-94-017-7267-9_14"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789401772662","9789401772679"],"references-count":40,"URL":"https:\/\/doi.org\/10.1007\/978-94-017-7267-9_14","relation":{},"subject":[],"published":{"date-parts":[[2017]]}}}