{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T21:25:01Z","timestamp":1743024301240,"version":"3.40.3"},"publisher-location":"Dordrecht","reference-count":31,"publisher":"Springer Netherlands","isbn-type":[{"type":"print","value":"9789401772662"},{"type":"electronic","value":"9789401772679"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-94-017-7267-9_33","type":"book-chapter","created":{"date-parts":[[2017,9,26]],"date-time":"2017-09-26T09:54:06Z","timestamp":1506419646000},"page":"1093-1126","source":"Crossref","is-referenced-by-count":0,"title":["Hardware\/Software Codesign Across Many Cadence Technologies"],"prefix":"10.1007","author":[{"given":"Grant","family":"Martin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Frank","family":"Schirrmeister","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yosinori","family":"Watanabe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,9,27]]},"reference":[{"key":"33_CR1","unstructured":"http:\/\/www.deepchip.com\/items\/0549-04.html"},{"key":"33_CR2","unstructured":"Andrews M, Hristov B (2015) Portable stimulus models for c\/SystemC, UVM and emulation. In: Design and verification conference and exhibition (DVCON). Accellera Systems Initiative"},{"key":"33_CR3","doi-asserted-by":"crossref","first-page":"173","DOI":"10.1007\/978-1-4020-9436-1_7","volume-title":"Hardware-dependent software: principles and practice","author":"S Augustine","year":"2009","unstructured":"Augustine\u00a0S, Gauthier\u00a0M, Leibson\u00a0S, Macliesh\u00a0P, Martin\u00a0G, Maydan\u00a0D, Nedeljkovic N, Wilson B (2009) Generation and use of an ASIP software tool chain. In: Ecker\u00a0W, M\u00fcller\u00a0W, D\u00f6mer\u00a0R (eds) Hardware-dependent software: principles and practice. Springer, Berlin, pp\u00a0173\u2013202"},{"key":"33_CR4","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4419-0965-7","volume-title":"ESL models and their application: electronic system level design and verification in practice","author":"B Bailey","year":"2010","unstructured":"Bailey B, Martin G (2010) ESL models and their application: electronic system level design and verification in practice. Springer, Boston"},{"key":"33_CR5","doi-asserted-by":"crossref","unstructured":"Bailey B, Martin G, Anderson T (eds) (2005) Taxonomies for the development and verification of digital systems. Springer, New York. The Virtual Socket Interface Alliance lasted from 1996 to 2008 but its archival web site is no longer functional as of 2015. This book may be all that is left of its work","DOI":"10.1007\/b104217"},{"key":"33_CR6","volume-title":"Electronic design automation for integrated circuits handbook","author":"F Balarin","year":"2016","unstructured":"Balarin F, Kondratyev A, Watanabe Y (2016) High level synthesis. In: Scheffer L, Lavagno L, Markov I, Martin G (eds) Electronic design automation for integrated circuits handbook, vol\u00a01, 2nd edn. CRC Press\/Taylor and Francis, Boca Raton","edition":"2"},{"key":"33_CR7","unstructured":"Bellas N, Katsavounidis I, Koziri M, Zacharis D (2009) Mapping the AVS video decoder on a heterogeneous dual-core SIMD processor. In: Design automation conference user track. IEEE\/ACM. \nhttp:\/\/www.dac.com\/46th\/proceedings\/slides\/07U_2.pdf"},{"key":"33_CR8","volume-title":"Denver IP acceleration leveraging enhanced debug","author":"M Bianchi","year":"2015","unstructured":"Bianchi M, Snyder T, Grabowski D (2015) Denver IP acceleration leveraging enhanced debug. In: CDNLive silicon valley. Cadence Design Systems"},{"key":"33_CR9","volume-title":"Mpsoc flow for multiformat video decoder based on configurable and extensible processors","author":"G Ezer","year":"2006","unstructured":"Ezer G, Moolenaar D (2006) Mpsoc flow for multiformat video decoder based on configurable and extensible processors. In: GSPx Conference"},{"key":"33_CR10","volume-title":"A practical guide to SysML","author":"S Friedenthal","year":"2014","unstructured":"Friedenthal S, Moore A, Steiner R (2014) A practical guide to SysML, 3rd edn. Morgan-Kaufmann, Boston","edition":"3"},{"issue":"2","key":"33_CR11","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1109\/40.848473","volume":"20","author":"R Gonzales","year":"2000","unstructured":"Gonzales R (2000) Xtensa: a configurable and extensible processor. IEEE Micro 20(2):60\u201370","journal-title":"IEEE Micro"},{"key":"33_CR12","volume-title":"System design with SystemC","author":"T Gr\u00f6tker","year":"2002","unstructured":"Gr\u00f6tker T, Liao S, Martin G, Swan S (2002) System design with SystemC. Kluwer Academic Publishers, Dordrecht"},{"key":"33_CR13","volume-title":"Functional and performance verification of SoC interconnects","author":"N Heaton","year":"2014","unstructured":"Heaton N, Behar A (2014) Functional and performance verification of SoC interconnects. Embed Comput Des. \nhttp:\/\/embedded-computing.com\/articles\/functional-performance-verification-soc-interconnects\/"},{"key":"33_CR14","volume-title":"Customizable embedded processors: design technologies and applications","author":"P Ienne","year":"2006","unstructured":"Ienne P, Leupers R (2006) Customizable embedded processors: design technologies and applications. Morgan Kaufmann\/Elsevier, San Francisco"},{"key":"33_CR15","volume-title":"Designing SOCs with configured cores: unleashing the Tensilica Xtensa and diamond cores","author":"S Leibson","year":"2006","unstructured":"Leibson S (2006) Designing SOCs with configured cores: unleashing the Tensilica Xtensa and diamond cores. Morgan Kaufmann\/Elsevier, San Francisco"},{"volume-title":"UML for SoC design","year":"2005","key":"33_CR16","unstructured":"Martin G, M\u00fcller W (eds) (2005) UML for SoC design. Springer, Heidelberg"},{"key":"33_CR17","doi-asserted-by":"crossref","first-page":"297","DOI":"10.1007\/978-1-4757-3281-8_25","volume-title":"System-on-chip methodologies and design languages","author":"G Martin","year":"2001","unstructured":"Martin G, Salefski B (2001) System level design for SoC\u2019s: a progress report \u2013 two years on. In: Ashenden P, Mermet J, Seepold R (eds) System-on-chip methodologies and design languages. Springer, Heidelberg, pp\u00a0297\u2013306"},{"issue":"4","key":"33_CR18","doi-asserted-by":"crossref","first-page":"18","DOI":"10.1109\/MDT.2009.83","volume":"26","author":"G Martin","year":"2009","unstructured":"Martin G, Smith G (2009) High-level synthesis: past, present, and future. IEEE Des Test 26(4):18\u201325","journal-title":"IEEE Des Test"},{"key":"33_CR19","volume-title":"Evolving voice and audio requirements for smartphones","author":"D Maydan","year":"2011","unstructured":"Maydan D (2011) Evolving voice and audio requirements for smartphones. In: Linley mobile conference. The Linley Group"},{"key":"33_CR20","volume-title":"Reducing time to point of interest with accelerated os boot","author":"L Melling","year":"2015","unstructured":"Melling L, Kaye R (2015) Reducing time to point of interest with accelerated os boot. In: CDNLive silicon valley. Cadence Design Systems"},{"key":"33_CR21","volume-title":"Electronic design automation for integrated circuits handbook, vol\u00a01","author":"P Mishra","year":"2006","unstructured":"Mishra P, Dutt N (2006) Processor modeling and design tools. In: Scheffer L, Lavagno L, Martin G (eds) Electronic design automation for integrated circuits handbook, vol\u00a01, 1st edn. CRC Press\/Taylor and Francis, Boca Raton","edition":"1"},{"volume-title":"Processor description languages","year":"2008","key":"33_CR22","unstructured":"Mishra P, Dutt N (eds) (2008) Processor description languages. Elsevier-Morgan Kaufmann, Amsterdam\/Boston"},{"key":"33_CR23","unstructured":"Murray D, Boylan S (2013) Lessons from the field: IP\/SoC integration techniques that work. In: Design and verification conference and exhibition (DVCON). Accellera Systems Initiative"},{"key":"33_CR24","doi-asserted-by":"crossref","unstructured":"Puig-Medina M, Ezer G, Konas P (2000) Verification of configurable processor cores. In: Proceedings of design automation conference (DAC). IEEE\/ACM, pp\u00a0184\u2013188","DOI":"10.1145\/337292.337527"},{"key":"33_CR25","volume-title":"Power\/performance breakthrough for LTE advanced handsets","author":"C Rowen","year":"2012","unstructured":"Rowen C (2012) Power\/performance breakthrough for LTE advanced handsets. In: Linley mobile conference. The Linley Group"},{"key":"33_CR26","volume-title":"Instruction set innovation in fourth generation vision DSPs","author":"C Rowen","year":"2015","unstructured":"Rowen C (2015) Instruction set innovation in fourth generation vision DSPs. In: Linley processor conference. The Linley Group"},{"key":"33_CR27","volume-title":"Engineering the complex SoC: fast, flexible design with configurable processors","author":"C Rowen","year":"2004","unstructured":"Rowen C, Leibson S (2004) Engineering the complex SoC: fast, flexible design with configurable processors. Prentice-Hall PTR, Upper Saddle River"},{"key":"33_CR28","unstructured":"Rowen C, Nuth P, Fiske S, Binning M, Khouri S (2012) A DSP architecture optimised for wireless baseband. In: International symposium on system-on-chip (ISSOC)"},{"key":"33_CR29","volume-title":"Baby you can drive my car: vision-based SoC architectures","author":"H Sanghavi","year":"2015","unstructured":"Sanghavi H (2015) Baby you can drive my car: vision-based SoC architectures. In: Linley processor conference. The Linley Group"},{"key":"33_CR30","volume-title":"Processor description languages","author":"H Sanghavi","year":"2008","unstructured":"Sanghavi H, Andrews N (2008) TIE: an ADL for designing application-specific instruction set extensions. In: Mishra P, Dutt N (eds) Processor description languages. Elsevier-Morgan Kaufmann, San Francisco"},{"key":"33_CR31","doi-asserted-by":"crossref","unstructured":"Wang A, Killian E, Maydan D, Rowen C (2001) Hardware\/software instruction set configurability for system-on-chip processors. In: Proceedings of design automation conference (DAC). IEEE\/ACM, pp\u00a0184\u2013188","DOI":"10.1145\/378239.378460"}],"container-title":["Handbook of Hardware\/Software Codesign"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-94-017-7267-9_33","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,9,27]],"date-time":"2017-09-27T08:04:29Z","timestamp":1506499469000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-94-017-7267-9_33"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789401772662","9789401772679"],"references-count":31,"URL":"https:\/\/doi.org\/10.1007\/978-94-017-7267-9_33","relation":{},"subject":[],"published":{"date-parts":[[2017]]}}}