{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:26:00Z","timestamp":1763724360954,"version":"3.40.3"},"publisher-location":"Dordrecht","reference-count":28,"publisher":"Springer Netherlands","isbn-type":[{"type":"print","value":"9789401772662"},{"type":"electronic","value":"9789401772679"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-94-017-7267-9_34","type":"book-chapter","created":{"date-parts":[[2017,9,26]],"date-time":"2017-09-26T09:54:06Z","timestamp":1506419646000},"page":"1127-1159","source":"Crossref","is-referenced-by-count":5,"title":["Synopsys Virtual Prototyping for Software Development and Early Architecture Analysis"],"prefix":"10.1007","author":[{"given":"Tim","family":"Kogel","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,9,27]]},"reference":[{"unstructured":"AMBA AXI and ACE Protocol Specification (2013). \n            http:\/\/infocenter.arm.com\/help\/index.jsp?topic=\/com.arm.doc.ihi0022e\/index.html","key":"34_CR1"},{"unstructured":"AMBA-PV Extensions to TLM Developer Guide (2015). \n            http:\/\/infocenter.arm.com\/help\/topic\/com.arm.doc.dui0846f\/DUI0846F_ambapv_extensions_to_tlm_2-0_dg.pdf","key":"34_CR2"},{"unstructured":"ARM Fast Models. \n            http:\/\/www.arm.com\/products\/tools\/models\/fast-models","key":"34_CR3"},{"volume-title":"TLM-driven design and verification methodology","year":"2010","unstructured":"Bailey B et al (eds) (2010) TLM-driven design and verification methodology. Cadence Design Systems, San Jose. \n            https:\/\/www.synopsys.com\/vpbook","key":"34_CR4"},{"key":"34_CR5","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-6127-9","volume-title":"Hardware-software co-design of embedded systems: the POLIS approach","author":"F Balarin","year":"1997","unstructured":"Balarin F et\u00a0al (1997) Hardware-software co-design of embedded systems: the POLIS approach. Kluwer Academic Publishers, Boston"},{"issue":"12","key":"34_CR6","doi-asserted-by":"publisher","first-page":"33","DOI":"10.1109\/MC.2007.443","volume":"40","author":"L Barroso","year":"2007","unstructured":"Barroso L, Holzle U (2007) The case for energy-proportional computing. Computer 40(12):33\u201337. doi: \n            10.1109\/MC.2007.443","journal-title":"Computer"},{"doi-asserted-by":"publisher","unstructured":"Datta S, Bonnet C, Nikaein N (2012) Android power management: current and future trends. In: 2012 first IEEE workshop on enabling technologies for smartphone and internet of things (ETSIoT), pp\u00a048\u201353. doi: \n            10.1109\/ETSIoT.2012.6311253","key":"34_CR7","DOI":"10.1109\/ETSIoT.2012.6311253"},{"unstructured":"Fadi\u00a0Aboud IC (2014) Balancing power performance and user experience using virtual prototyping. In: Proceedings of the synopsys users group conference (SNUG), Israel. \n            https:\/\/www.synopsys.com\/news\/pubs\/snug\/2014\/israel\/B2_Aboud_pres_user.pdf","key":"34_CR8"},{"doi-asserted-by":"publisher","unstructured":"Fischer B, Cech C, Muhr H (2014) Power modeling and analysis in early design phases. In: Proceedings of design, automation and test in Europe conference and exhibition (DATE), pp\u00a01\u20136. doi: \n            10.7873\/DATE.2014.210","key":"34_CR9","DOI":"10.7873\/DATE.2014.210"},{"key":"34_CR10","volume-title":"Low power methodology manual for system-on-chip design","author":"D Flynn","year":"2007","unstructured":"Flynn D, Aitken R, Gibbons A, Shi K (2007) Low power methodology manual for system-on-chip design. Springer, New York"},{"key":"34_CR11","volume-title":"Standard for Design and Verification of Low-Power Integrated Circuits","author":"IEEE","year":"2015","unstructured":"IEEE Standard for Design and Verification of Low-Power Integrated Circuits (2015). \n            http:\/\/standards.ieee.org\/getieee\/1801\/download\/1801-2015.pdf"},{"key":"34_CR12","volume-title":"Standard for Standard SystemC Language Reference Manual","author":"IEEE","year":"2011","unstructured":"IEEE Standard for Standard SystemC Language Reference Manual (2011). \n            http:\/\/standards.ieee.org\/getieee\/1666\/download\/1666-2011.pdf"},{"doi-asserted-by":"publisher","unstructured":"Kempf T, Doerper M, Leupers R, Ascheid G, Meyr H, Kogel T, Vanthournout B (2005) A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms. In: Proceedings of design, automation and test in Europe, vol\u00a02, pp\u00a0876\u2013881. doi: \n            10.1109\/DATE.2005.21","key":"34_CR13","DOI":"10.1109\/DATE.2005.21"},{"key":"34_CR14","doi-asserted-by":"crossref","first-page":"71","DOI":"10.1007\/1-4020-5138-7_6","volume-title":"Platform based design at the electronic system level","author":"T Kogel","year":"2006","unstructured":"Kogel T (2006) Peripheral modeling for platform driven ESL design. In: Burton M, Morawiec A (eds) Platform based design at the electronic system level. Springer, Dordrecht, pp\u00a071\u201385"},{"unstructured":"Kogel T (2013) Designing the right architecture, SoC interconnect and memory optimization with synopsys platform architect. Synopsys whitepaper. \n            https:\/\/www.synopsys.com\/cgi-bin\/proto\/pdfdla\/pdfr1.cgi?file=pa_soc_v4_wp.pdf","key":"34_CR15"},{"unstructured":"Kogel T (2016) Optimizing DDR memory subsystem efficiency, Part 1: the unpredictable memory bottleneck. Synopsys whitepaper. \n            https:\/\/www.synopsys.com\/cgi-bin\/proto\/pdfdla\/pdfr1.cgi?file=optimizing-ddr-efficiency-p1-wp.pdf","key":"34_CR16"},{"unstructured":"Kogel T (2016) Optimizing DDR memory subsystem efficiency, Part 2: case study. Synopsys whitepaper. \n            https:\/\/www.synopsys.com\/cgi-bin\/proto\/pdfdla\/pdfr1.cgi?file=optimizing-ddr-efficiency-p2-wp.pdf","key":"34_CR17"},{"key":"34_CR18","volume-title":"Integrated system-level modeling of network-on-chip enabled multi-processor platforms","author":"T Kogel","year":"2005","unstructured":"Kogel T et al (2005) Integrated system-level modeling of network-on-chip enabled multi-processor platforms. Springer, Dordrecht"},{"issue":"2","key":"34_CR19","doi-asserted-by":"publisher","first-page":"133","DOI":"10.1007\/s10617-011-9075-5","volume":"15","author":"J-J Lecler","year":"2011","unstructured":"Lecler J-J, Baillieu G (2011) Application driven network-on-chip architecture exploration & refinement for a complex SoC. Des Autom Embed Syst 15(2):133\u2013158. doi: \n            10.1007\/s10617-011-9075-5","journal-title":"Des Autom Embed Syst"},{"unstructured":"Patel S, Sood B, Semiconductor F (2014) Quick, re-usable and cost effective approach to create accurate models using synopsys platform architect framework for early system level performance analysis. In: Proceedings of the synopsys users group conference (SNUG), India. \n            http:\/\/www.synopsys.com\/news\/pubs\/snug\/2014\/India\/paper_sood.pdf","key":"34_CR20"},{"issue":"1","key":"34_CR21","doi-asserted-by":"crossref","first-page":"9","DOI":"10.4271\/2012-01-0001","volume":"5","author":"V Reyes","year":"2012","unstructured":"Reyes V (2012) Virtualized fault injection methods in the context of the ISO 26262 standard. SAE Int J Passenger Cars Electron Electr Syst 5(1):9\u201316","journal-title":"SAE Int J Passenger Cars Electron Electr Syst"},{"doi-asserted-by":"publisher","unstructured":"Schurmans S, Zhang D, Auras D, Leupers R, Ascheid G, Chen X, Wang L (2013) Creation of ESL power models for communication architectures using automatic calibration. In: 2013 50th ACM\/EDAC\/IEEE design automation conference (DAC), pp\u00a01\u20136. doi: \n            10.1145\/2463209.2488804","key":"34_CR22","DOI":"10.1145\/2463209.2488804"},{"unstructured":"Schutter TD (ed) (2014) Better software. Faster! best practices in virtual prototyping. Synopsys Press. \n            https:\/\/www.synopsys.com\/vpbook","key":"34_CR23"},{"unstructured":"Skrzeszewski TK, Intel Corp. (2015) ATOM mobile SoC performance and power architecture exploration. In: Synopsys users group conference (SNUG), Santa Clara. \n            http:\/\/www.synopsys.com\/news\/pubs\/snug\/2015\/silicon-valley\/mb08_skrzeszewski_paper.pdf","key":"34_CR24"},{"unstructured":"Synopsys DW TLM library. \n            http:\/\/www.synopsys.com\/Prototyping\/VirtualPrototyping\/VPModels\/Pages\/DW-TLM-Library.aspx","key":"34_CR25"},{"doi-asserted-by":"publisher","unstructured":"Teich J (2012) Hardware\/software codesign: the past, the present, and predicting the future. Proc IEEE 100(Special Centennial Issue):1411\u20131430. doi: \n            10.1109\/JPROC.2011.2182009","key":"34_CR26","DOI":"10.1109\/JPROC.2011.2182009"},{"unstructured":"The SystemC Modeling Library (SCML). \n            http:\/\/www.synopsys.com\/cgi-bin\/slcw\/kits\/reg.cgi","key":"34_CR27"},{"unstructured":"Tool Command Language (TCL). \n            http:\/\/www.tcl.tk","key":"34_CR28"}],"container-title":["Handbook of Hardware\/Software Codesign"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-94-017-7267-9_34","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,9,27]],"date-time":"2017-09-27T08:04:40Z","timestamp":1506499480000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-94-017-7267-9_34"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789401772662","9789401772679"],"references-count":28,"URL":"https:\/\/doi.org\/10.1007\/978-94-017-7267-9_34","relation":{},"subject":[],"published":{"date-parts":[[2017]]}}}