{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T14:44:53Z","timestamp":1742913893404,"version":"3.40.3"},"publisher-location":"Singapore","reference-count":25,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811022081"},{"type":"electronic","value":"9789811022098"}],"license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016]]},"DOI":"10.1007\/978-981-10-2209-8_1","type":"book-chapter","created":{"date-parts":[[2016,8,7]],"date-time":"2016-08-07T22:39:56Z","timestamp":1470609596000},"page":"1-14","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["An OS-level Data Distribution Method in DRAM-PCM Hybrid Memory"],"prefix":"10.1007","author":[{"given":"Hongbin","family":"Zhang","sequence":"first","affiliation":[]},{"given":"Jie","family":"Fan","sequence":"additional","affiliation":[]},{"given":"Jiwu","family":"Shu","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,8,9]]},"reference":[{"key":"1_CR1","unstructured":"Drem DDR3 technology. \n                  http:\/\/www.micron.com\/products\/dram\/ddr3-sdram\/\n                  \n                . Accessed 1 Jul 2015"},{"key":"1_CR2","unstructured":"Pin - a dynamic binary instrumentation tool. \n                  https:\/\/software.intel.com\/en-us\/articles\/pin-a-dynamic-binary-instrumentation-tool\n                  \n                . Accessed 1 Jul 2015"},{"key":"1_CR3","unstructured":"The parsec benchmark suite. \n                  http:\/\/parsec.cs.princeton.edu\/index.htm\n                  \n                . Accessed 10 Jan 2016"},{"key":"1_CR4","unstructured":"Splash-2 benchmarks suite. \n                  http:\/\/www.capsl.udel.edu\/splash\n                  \n                . Accessed 10 Jan 2016"},{"key":"1_CR5","doi-asserted-by":"crossref","unstructured":"Bathen, L.A., et al.: HaVOC: a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and Non-Volatile Memories. ACM (2012)","DOI":"10.1145\/2228360.2228438"},{"key":"1_CR6","doi-asserted-by":"publisher","first-page":"2","DOI":"10.1145\/1555815.1555758","volume":"37","author":"BC Lee","year":"2009","unstructured":"Lee, B.C., et al.: Architecting phase change memory as a scalable dram alternative. ACM SIGARCH Comput. Archit. News 37, 2\u201313 (2009)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"1_CR7","doi-asserted-by":"publisher","first-page":"99","DOI":"10.1145\/1785414.1785441","volume":"53","author":"BC Lee","year":"2010","unstructured":"Lee, B.C., et al.: Phase change memory architecture and the quest for scalability. Commun. ACM 53, 99\u2013106 (2010)","journal-title":"Commun. ACM"},{"issue":"1","key":"1_CR8","doi-asserted-by":"publisher","first-page":"143","DOI":"10.1109\/MM.2010.24","volume":"30","author":"BC Lee","year":"2010","unstructured":"Lee, B.C., et al.: phase-change technology and the future of main memory. IEEE Micro 30(1), 143 (2010)","journal-title":"IEEE Micro"},{"key":"1_CR9","doi-asserted-by":"crossref","unstructured":"Bienia, C., et al.: PARSEC vs. SPLASH-2: a quantitative comparison of two multithreaded benchmark suites on chip-multiprocessors. In: 4th International Symposium on Workload Characterization (2008)","DOI":"10.1109\/IISWC.2008.4636090"},{"key":"1_CR10","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1145\/1064978.1065034","volume":"40","author":"CK Luk","year":"2005","unstructured":"Luk, C.K., et al.: Pin: building customized program analysis tools with dynamic instrumentation. ACM SIGPLAN Not. 40, 190\u2013200 (2005)","journal-title":"ACM SIGPLAN Not."},{"key":"1_CR11","volume-title":"Understanding the Linux Kernel","author":"DP Bovet","year":"2005","unstructured":"Bovet, D.P., et al.: Understanding the Linux Kernel. O\u2019Reilly Media, Sebastopol (2005)"},{"key":"1_CR12","unstructured":"Bedeschi, F., et al.: An 8Mb demonstrator for high-density 1.8V Phase-Change Memories. In: Proceedings of IEEE Symp on VLSI Circuits (2004)"},{"key":"1_CR13","doi-asserted-by":"crossref","unstructured":"Dhiman, G., et al.: PDRAM: a hybrid PRAM and DRAM main memory system. In: Proceedings of 47th ACM Design Automation International Conference (DAC) (2009)","DOI":"10.1145\/1629911.1630086"},{"key":"1_CR14","doi-asserted-by":"crossref","unstructured":"Yoon, H.B., et al.: Row buffer locality-aware data placement in hybrid memories. SAFARI Technical report (2011)","DOI":"10.1109\/ICCD.2012.6378661"},{"key":"1_CR15","doi-asserted-by":"crossref","unstructured":"Yoon, H.B., et al.: Row buffer locality aware caching policies for hybrid memories. In: IEEE ICCD (2012)","DOI":"10.1109\/ICCD.2012.6378661"},{"key":"1_CR16","doi-asserted-by":"publisher","first-page":"1094","DOI":"10.1109\/TVLSI.2012.2202700","volume":"21","author":"J Hu","year":"2012","unstructured":"Hu, J., et al.: Data allocation optimization for hybrid scratch pad memory with SRAM and nonvolatile memory. Proc. IEEE Trans. VLSI 21, 1094\u20131102 (2012)","journal-title":"Proc. IEEE Trans. VLSI"},{"key":"1_CR17","unstructured":"von Neumann, J.: The general and logical theory of automata. Cerebral mechanisms in behavior (1951)"},{"key":"1_CR18","doi-asserted-by":"publisher","first-page":"61","DOI":"10.1109\/L-CA.2012.2","volume":"11","author":"J Meza","year":"2012","unstructured":"Meza, J., et al.: Enabling efficient and scalable hybrid memories using fine-granularity DRAM cache management. Comput. Archit. Lett. 11, 61\u201364 (2012)","journal-title":"Comput. Archit. Lett."},{"key":"1_CR19","doi-asserted-by":"crossref","unstructured":"Ramos, L.E., et al.: Page placement in hybrid memory systems. In: ACM ICS (2011)","DOI":"10.1145\/1995896.1995911"},{"key":"1_CR20","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1145\/1555815.1555760","volume":"37","author":"MK Qureshi","year":"2009","unstructured":"Qureshi, M.K., et al.: Scalable high performance main memory system using phase-change memory technology. ACM SIGARCH Comput. Archit. News 37, 24\u201333 (2009)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"1_CR21","doi-asserted-by":"crossref","unstructured":"Qureshi, M.K., et al.: Phase Change Memory: From Devices to Systems. Synthesis Lectures on Computer Architecture (2011)","DOI":"10.2200\/S00381ED1V01Y201109CAC018"},{"key":"1_CR22","doi-asserted-by":"crossref","unstructured":"Mutlu, O., et al.: Memory scaling: a systems architecture perspective. In: Memory Workshop (IMW) (2013)","DOI":"10.1109\/IMW.2013.6582088"},{"key":"1_CR23","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1145\/1555815.1555759","volume":"37","author":"P Zhou","year":"2009","unstructured":"Zhou, P., et al.: A durable and energy efficient main memory using phase change memory technology. ACM SIGARCH Comput. Archit. News 37, 14\u201323 (2009)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"1_CR24","doi-asserted-by":"crossref","unstructured":"Bheda, R.A., et al.: Energy efficient phase change memory based main memory for future high performance systems. In: Proceedings of IEEE on International Green Computing Conference and Workshops (2011)","DOI":"10.1109\/IGCC.2011.6008569"},{"key":"1_CR25","unstructured":"T, L., et al.: Power-aware variable partitioning for DSPS with hybrid PRAM and DRAM main memory. In: Design Automation Conference (DAC) (2011)"}],"container-title":["Communications in Computer and Information Science","Advanced Computer Architecture"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-2209-8_1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,20]],"date-time":"2019-05-20T23:10:16Z","timestamp":1558393816000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-2209-8_1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"ISBN":["9789811022081","9789811022098"],"references-count":25,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-2209-8_1","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2016]]},"assertion":[{"value":"9 August 2016","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ACA","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Conference on Advanced Computer Architecture","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Weihai","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"China","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2016","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"22 August 2016","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"23 August 2016","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"aca2016","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}