{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T13:21:48Z","timestamp":1725888108875},"publisher-location":"Singapore","reference-count":14,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811050404"},{"type":"electronic","value":"9789811050411"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-981-10-5041-1_59","type":"book-chapter","created":{"date-parts":[[2017,5,13]],"date-time":"2017-05-13T07:14:39Z","timestamp":1494659679000},"page":"361-366","source":"Crossref","is-referenced-by-count":0,"title":["On Bypassing Page Cache for Block Devices on Storage Class Memory"],"prefix":"10.1007","author":[{"given":"Jin Baek","family":"Kwon","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,5,14]]},"reference":[{"key":"59_CR1","doi-asserted-by":"crossref","first-page":"501","DOI":"10.1038\/nnano.2011.96","volume":"6","author":"RE Simpson","year":"2011","unstructured":"Simpson, R.E., Fons, P., Kolobov, A.V., Fukaya, T., Krbal, M., Tominaga, J.: Interfacial phase change memory. Nat. Nanotechnol. 6, 501\u2013505 (2011)","journal-title":"Nat. Nanotechnol."},{"issue":"6","key":"59_CR2","doi-asserted-by":"crossref","first-page":"1873","DOI":"10.1109\/TMAG.2010.2042041","volume":"46","author":"E Chen","year":"2010","unstructured":"Chen, E., Apalkov, D., Diao, Z., et al.: Advances and future prospects of spin-transfer torque random access memory. IEEE Trans. Magn. 46(6), 1873\u20131878 (2010)","journal-title":"IEEE Trans. Magn."},{"key":"59_CR3","doi-asserted-by":"crossref","unstructured":"Xue, C.J, Zhang, Y., Chen, Y., Sun, G., Yang, J.J., Li, H.: Emerging non-volatile memories: opportunities and challenges. In: Proceedings of the International Conference on Hardware\/Software Codesign and System Synthesis (CODES\u00a0+\u00a0ISSS) (2011)","DOI":"10.1145\/2039370.2039420"},{"key":"59_CR4","doi-asserted-by":"crossref","unstructured":"Dhiman, G., Ayoub, R., Rosing, T.: PDRAM: a hybrid PRAM and DRAM main memory system. In: Proceedings of the Design Automation Conference (DAC) (2009)","DOI":"10.1145\/1629911.1630086"},{"key":"59_CR5","doi-asserted-by":"crossref","unstructured":"Qureshi, M., Srinivasan, V., Rivers, J.A.: Scalable high performance main memory system using phase-change memory technology. In: Proceedings of the International Symposium on Computer Architecture (ISCA), Austin, TX (2009)","DOI":"10.1145\/1555754.1555760"},{"issue":"2","key":"59_CR6","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1109\/L-CA.2012.2","volume":"11","author":"J Meza","year":"2012","unstructured":"Meza, J., Chang, J., Yoon, H., Mutlu, O., Ranganathan, P.: Enabling efficient and scalable hybrid memories using fine-granularity DRAM cache management. IEEE Comput. Archit. Lett. 11(2), 61\u201364 (2012)","journal-title":"IEEE Comput. Archit. Lett."},{"key":"59_CR7","doi-asserted-by":"crossref","unstructured":"Lee, B.C., Ipek, E., Mutlu, O., Burger, D.: Architecting phase change memory as a scalable DRAM alternative. In: Proceedings of the International Symposium on Computer Architecture (ISCA), Austin, TX (2009)","DOI":"10.1145\/1555754.1555758"},{"key":"59_CR8","unstructured":"Bailey, K., Ceze, L., Gribble, S.D., Levy, H.M.: Operating system implications of fast, cheap, non-volatile memory. In: Proceedings of the Workshops on Hot Topics in Operating Systems (HotOS) (2011)"},{"key":"59_CR9","unstructured":"Mogul, J.C., Argollo, E., Shah, M., Faraboschi, P.: Operating system support for NVM\u00a0+\u00a0DRAM hybrid main memory. In: Proceedings of the Workshops on Hot Topics in Operating Systems (HotOS) (2009)"},{"key":"59_CR10","unstructured":"Meza, J., Luo, Y., Khan, S., Zhao, J., Xie, Y., Mutlu, O.; A case for efficient hardware\/software cooperative management of storage and memory. In: Proceedings of the Workshop on Energy-Efficient Design (WEED) (2013)"},{"key":"59_CR11","doi-asserted-by":"crossref","unstructured":"Moraru, I., Andersen, D.G., Kaminsky, M., Tolia, N., Ranganathan, P., Binkert, N.: Consistent, durable, and safe memory management for byte-addressable non-volatile main memory. In: Proceedings of the Conference on Timely Results on Operating Systems (TRIOS) (2013)","DOI":"10.1145\/2524211.2524216"},{"key":"59_CR12","doi-asserted-by":"crossref","unstructured":"Chen, F., Mesnier, M.P., Hahn, S.: A protected block device for persistent memory. In: Proceedings of the Symposium on Mass Storage Systems and Technologies (2014)","DOI":"10.1109\/MSST.2014.6855541"},{"key":"59_CR13","unstructured":"Tarasov, V., Zadok, E., Shepler, S.: Filebench: a flexible framework for file system benchmarking. login: USENIX Mag. 41(1), Spring 2016"},{"key":"59_CR14","unstructured":"Lameter, C.: Limit the size of the page cache. LWN.net, January 2007. \nhttps:\/\/lwn.net\/Articles\/218890"}],"container-title":["Lecture Notes in Electrical Engineering","Advanced Multimedia and Ubiquitous Engineering"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-5041-1_59","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,5,13]],"date-time":"2017-05-13T07:28:48Z","timestamp":1494660528000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-5041-1_59"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789811050404","9789811050411"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-5041-1_59","relation":{},"ISSN":["1876-1100","1876-1119"],"issn-type":[{"type":"print","value":"1876-1100"},{"type":"electronic","value":"1876-1119"}],"subject":[],"published":{"date-parts":[[2017]]}}}