{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T02:45:20Z","timestamp":1725936320043},"publisher-location":"Singapore","reference-count":9,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811074691"},{"type":"electronic","value":"9789811074707"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-981-10-7470-7_30","type":"book-chapter","created":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T18:17:13Z","timestamp":1513793833000},"page":"299-312","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Energy-Efficient VLSI Architecture &amp; Implementation of Bi-modal Multi-banked Register-File Organization"],"prefix":"10.1007","author":[{"given":"Sumanth","family":"Gudaparthi","sequence":"first","affiliation":[]},{"given":"Rahul","family":"Shrestha","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,12,21]]},"reference":[{"key":"30_CR1","series-title":"A Quantitative Approach","volume-title":"Computer Architecture","author":"JL Hennessy","year":"2011","unstructured":"Hennessy, J.L., Patterson, D.A.: Computer Architecture. A Quantitative Approach, 5th edn. Morgan Kaufmann Publishers Inc., San Francisco (2011)","edition":"5"},{"key":"30_CR2","doi-asserted-by":"crossref","unstructured":"Ayala, J.L., Lopez-Vallejo, M., Veidenbaum, A., Lopez, C.A.: Energy aware register file implementation through instruction predecode. In: IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 86\u201396 (2003)","DOI":"10.1109\/ASAP.2003.1212832"},{"key":"30_CR3","doi-asserted-by":"crossref","first-page":"2513","DOI":"10.1109\/TVLSI.2013.2293702","volume":"22","author":"H Tabkhi","year":"2014","unstructured":"Tabkhi, H., Schirner, G.: Application-guided power gating reducing register file static power. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22, 2513\u20132526 (2014)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"30_CR4","doi-asserted-by":"crossref","first-page":"82","DOI":"10.1109\/TC.2007.70785","volume":"57","author":"D Balkan","year":"2008","unstructured":"Balkan, D., Sharkey, J., Ponomarev, D., Ghose, K.: Predicting and exploiting transient values for reducing register file pressure and energy consumption. IEEE Trans. Comput. 57, 82\u201395 (2008)","journal-title":"IEEE Trans. Comput."},{"key":"30_CR5","doi-asserted-by":"crossref","unstructured":"Tseng, J.H., Asanovic, K.: Energy-efficient register access. In: 13th Symposium on Integrated Circuits and Systems Design, pp. 377\u2013382 (2000)","DOI":"10.1109\/SBCCI.2000.876058"},{"key":"30_CR6","doi-asserted-by":"crossref","unstructured":"Gonzalez, R., Cristal, A., Ortega, D., Veidenbaum, A., Valero, M.: A content aware integer register file organization. In: 31st Annual International Symposium on Computer Architecture, pp. 314\u2013324 (2004)","DOI":"10.1109\/ISCA.2004.1310784"},{"key":"30_CR7","doi-asserted-by":"crossref","unstructured":"Zeng, H., Binghamton, N.Y., Ghose, K.: Register file caching for energy efficiency. In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, pp. 244\u2013249 (2006)","DOI":"10.1145\/1165573.1165633"},{"key":"30_CR8","doi-asserted-by":"crossref","unstructured":"Yung, R., Wilhelm, N.C.: Caching processor general registers. In: IEEE International Conference on Computer Design: VLSI in Computers and Processors (1995)","DOI":"10.1109\/ICCD.1995.528826"},{"key":"30_CR9","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1109\/L-CA.2009.45","volume":"8","author":"J Balfour","year":"2009","unstructured":"Balfour, J., Harting, R.C., Dally, W.J.: Operand registers and explicit operand forwarding. IEEE Comput. Archit. Lett. 8, 60\u201363 (2009)","journal-title":"IEEE Comput. Archit. Lett."}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-7470-7_30","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T18:29:17Z","timestamp":1513794557000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-7470-7_30"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789811074691","9789811074707"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-7470-7_30","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2017]]}}}