{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T02:45:20Z","timestamp":1725936320637},"publisher-location":"Singapore","reference-count":10,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811074691"},{"type":"electronic","value":"9789811074707"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-981-10-7470-7_32","type":"book-chapter","created":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T18:17:13Z","timestamp":1513793833000},"page":"324-336","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["ACAM: Application Aware Adaptive Cache Management for Shared LLC"],"prefix":"10.1007","author":[{"given":"Sujit Kr","family":"Mahto","sequence":"first","affiliation":[]},{"family":"Newton","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,12,21]]},"reference":[{"issue":"5","key":"32_CR1","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1145\/1941487.1941507","volume":"54","author":"S Borkar","year":"2011","unstructured":"Borkar, S., Chien, A.A.: The future of microprocessors. Commun. ACM 54(5), 67\u201377 (2011)","journal-title":"Commun. ACM"},{"key":"32_CR2","doi-asserted-by":"crossref","unstructured":"Carlson, T.E., Heirman, W., Eeckhout, L.: Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation. In: Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis, p. 52. ACM (2011)","DOI":"10.1145\/2063384.2063454"},{"issue":"4","key":"32_CR3","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1186736.1186737","volume":"34","author":"JL Henning","year":"2006","unstructured":"Henning, J.L.: SPEC CPU2006 benchmark descriptions. ACM SIGARCH Comput. Archit. News 34(4), 1\u201317 (2006)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"32_CR4","unstructured":"Intel: Intel Core i7 Processor. http:\/\/www.intel.com\/products\/processor\/corei7\/specifications.htm"},{"key":"32_CR5","doi-asserted-by":"crossref","unstructured":"Jaleel, A., Hasenplaugh, W., Qureshi, M., Sebot, J., Steely Jr., S., Emer, J.: Adaptive insertion policies for managing shared caches. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pp. 208\u2013219. ACM (2008)","DOI":"10.1145\/1454115.1454145"},{"key":"32_CR6","doi-asserted-by":"crossref","unstructured":"Jaleel, A., Theobald, K.B., Steely Jr., S.C., Emer, J.: High performance cache replacement using re-reference interval prediction (RRIP). In: ACM SIGARCH Computer Architecture News, vol. 38, pp. 60\u201371. ACM (2010)","DOI":"10.1145\/1816038.1815971"},{"key":"32_CR7","doi-asserted-by":"crossref","unstructured":"Lathigara, P., Balachandran, S., Singh, V.: Application behavior aware re-reference interval prediction for shared LLC. In: Proceedings of the 33rd IEEE International Conference on Computer Design (ICCD), pp. 172\u2013179. IEEE (2015)","DOI":"10.1109\/ICCD.2015.7357099"},{"key":"32_CR8","doi-asserted-by":"crossref","unstructured":"Qureshi, M.K., Jaleel, A., Patt, Y.N., Steely Jr., S.C., Emer, J.: Adaptive insertion policies for high performance caching. In: ACM SIGARCH Computer Architecture News, vol. 35, pp. 381\u2013391. ACM (2007)","DOI":"10.1145\/1250662.1250709"},{"key":"32_CR9","doi-asserted-by":"crossref","unstructured":"Qureshi, M.K., Patt, Y.N.: Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In: Proceedings of the 39th Annual IEEE\/ACM International Symposium on Microarchitecture, IEEE Computer Society (2006) 423\u2013432","DOI":"10.1109\/MICRO.2006.49"},{"key":"32_CR10","doi-asserted-by":"crossref","unstructured":"Wu, C.J., Jaleel, A., Martonosi, M., Steely Jr., S.C., Emer, J.: Pacman: Prefetch-aware cache management for high performance caching. In: Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 442\u2013453. ACM (2011)","DOI":"10.1145\/2155620.2155672"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-7470-7_32","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,8]],"date-time":"2019-10-08T10:02:30Z","timestamp":1570528950000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-7470-7_32"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789811074691","9789811074707"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-7470-7_32","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2017]]}}}