{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,9]],"date-time":"2025-12-09T15:41:40Z","timestamp":1765294900338},"publisher-location":"Singapore","reference-count":8,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811074691"},{"type":"electronic","value":"9789811074707"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-981-10-7470-7_33","type":"book-chapter","created":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T18:17:13Z","timestamp":1513793833000},"page":"337-344","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs"],"prefix":"10.1007","author":[{"given":"N. S.","family":"Aswathy","sequence":"first","affiliation":[]},{"given":"R. S. Reshma","family":"Raj","sequence":"additional","affiliation":[]},{"given":"Abhijit","family":"Das","sequence":"additional","affiliation":[]},{"given":"John","family":"Jose","sequence":"additional","affiliation":[]},{"given":"V. R.","family":"Josna","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,12,21]]},"reference":[{"key":"33_CR1","doi-asserted-by":"crossref","unstructured":"Baydal, E., et al.: A congestion control mechanism for wormhole networks. In: Ninth Euromicro Workshop on Parallel and Distributed Processing. IEEE, pp. 19\u201326 (2001)","DOI":"10.1109\/EMPDP.2001.904965"},{"key":"33_CR2","doi-asserted-by":"crossref","unstructured":"Thottethodi, M., et al.: Self-tuned congestion control for multiprocessor networks. In: The Seventh International Symposium on High-Performance Computer Architecture, HPCA, pp. 107\u2013118. IEEE (2001)","DOI":"10.1109\/HPCA.2001.903256"},{"issue":"3","key":"33_CR3","doi-asserted-by":"crossref","first-page":"335","DOI":"10.1145\/1735971.1736058","volume":"45","author":"E Ebrahimi","year":"2010","unstructured":"Ebrahimi, E., et al.: Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. ACM SIGPLAN Not. 45(3), 335\u2013346 (2010). ACM","journal-title":"ACM SIGPLAN Not."},{"key":"33_CR4","unstructured":"Ausavarungnirun, R., et al.: Adaptive cluster throttling: improving high-load performance in bufferless on-chip networks. Computer Architecture Lab (CALCM), Carnegie Mellon University, SAFARI Technical Report TR-2011-006 (2011)"},{"issue":"4","key":"33_CR5","doi-asserted-by":"crossref","first-page":"407","DOI":"10.1145\/2377677.2377757","volume":"42","author":"GP Nychis","year":"2012","unstructured":"Nychis, G.P., et al.: On-chip networks from a networking perspective: congestion and scalability in many-core interconnects. ACM SIGCOMM Comput. Commun. Rev. 42(4), 407\u2013418 (2012)","journal-title":"ACM SIGCOMM Comput. Commun. Rev."},{"key":"33_CR6","doi-asserted-by":"crossref","unstructured":"Chang, K.K.-W., et al.: HAT: heterogeneous adaptive throttling for on-chip networks. In: IEEE 24th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pp. 9\u201318. IEEE (2012)","DOI":"10.1109\/SBAC-PAD.2012.44"},{"key":"33_CR7","doi-asserted-by":"crossref","unstructured":"Jiang, N., et al.: A detailed and flexible cycle-accurate network-on-chip simulator. In: 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 86\u201396. IEEE (2013)","DOI":"10.1109\/ISPASS.2013.6557149"},{"issue":"2","key":"33_CR8","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","volume":"39","author":"N Binkert","year":"2011","unstructured":"Binkert, N., et al.: The gem5 simulator. ACM SIGARCH Comput. Architect. News 39(2), 1\u20137 (2011)","journal-title":"ACM SIGARCH Comput. Architect. News"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-7470-7_33","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T18:30:08Z","timestamp":1513794608000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-7470-7_33"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789811074691","9789811074707"],"references-count":8,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-7470-7_33","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2017]]}}}