{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T02:45:05Z","timestamp":1725936305162},"publisher-location":"Singapore","reference-count":11,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811074691"},{"type":"electronic","value":"9789811074707"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-981-10-7470-7_4","type":"book-chapter","created":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T13:17:13Z","timestamp":1513775833000},"page":"36-47","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder"],"prefix":"10.1007","author":[{"given":"K.","family":"Dheepika","sequence":"first","affiliation":[]},{"given":"K. S.","family":"Jevasankari","sequence":"additional","affiliation":[]},{"given":"Vippin","family":"Chandhar","sequence":"additional","affiliation":[]},{"given":"Binsu J.","family":"Kailath","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,12,21]]},"reference":[{"key":"4_CR1","doi-asserted-by":"crossref","unstructured":"Barakat, M., Saad, W., Shokair, M., Elkordy, M.: Implementation of efficient portable low delay adder using FPGA. In: 28th International Conference on Microelectronics ICM (2016)","DOI":"10.1109\/ICM.2016.7847859"},{"key":"4_CR2","doi-asserted-by":"crossref","unstructured":"Suganya, R., Meganathan, D.: High performance VLSI adders. In: 3rd International Conference on Signal Processing, Communication and Networking ICSCN (2015)","DOI":"10.1109\/ICSCN.2015.7219919"},{"key":"4_CR3","volume-title":"Contemporary Logic Design","author":"RH Katz","year":"1994","unstructured":"Katz, R.H.: Contemporary Logic Design. Benjamin Publishing Co., CA (1994)"},{"key":"4_CR4","doi-asserted-by":"crossref","first-page":"156","DOI":"10.1147\/rd.252.0156","volume":"25","author":"H Ling","year":"1981","unstructured":"Ling, H.: High-speed binary adder. IBM J. Res. Dev. 25, 156\u2013166 (1981)","journal-title":"IBM J. Res. Dev."},{"key":"4_CR5","doi-asserted-by":"crossref","unstructured":"Saji Antony, M., Sri Ranjani Prasanthi, S., Indu, S., Pandey, R.: Design of high speed Vedic multiplier using multiplexer based adder. In: International Conference on Control Communication & Computing India ICCC (2015)","DOI":"10.1109\/ICCC.2015.7432938"},{"key":"4_CR6","first-page":"349","volume":"19","author":"L Dadda","year":"1965","unstructured":"Dadda, L.: Some schemes for parallel multipliers. Alta Freq. 19, 349\u2013356 (1965)","journal-title":"Alta Freq."},{"key":"4_CR7","doi-asserted-by":"crossref","unstructured":"Ling, H.: High speed binary parallel adder. IEEE Trans. Electron. Comput. EC15, 799\u2013802 (1966)","DOI":"10.1109\/PGEC.1966.264571"},{"key":"4_CR8","doi-asserted-by":"crossref","first-page":"678","DOI":"10.1109\/T-C.1971.223325","volume":"C20","author":"TC Chen","year":"1971","unstructured":"Chen, T.C.: A binary multiplication scheme based on squaring. IEEE Trans. Comput. C20, 678\u2013680 (1971)","journal-title":"IEEE Trans. Comput."},{"key":"4_CR9","doi-asserted-by":"crossref","first-page":"957","DOI":"10.1109\/TC.1976.1674723","volume":"C25","author":"T Jayashree","year":"1976","unstructured":"Jayashree, T., Basu, D.: On binary multiplication using the quarter square algorithm. IEEE Trans. Comput. C25, 957\u2013960 (1976)","journal-title":"IEEE Trans. Comput."},{"key":"4_CR10","doi-asserted-by":"crossref","first-page":"258","DOI":"10.1109\/TC.1980.1675558","volume":"C29","author":"EL Johnson","year":"1980","unstructured":"Johnson, E.L.: A digital quarter square multiplier. IEEE Trans. Comput. C29, 258\u2013261 (1980)","journal-title":"IEEE Trans. Comput."},{"key":"4_CR11","doi-asserted-by":"crossref","first-page":"706","DOI":"10.1109\/T-C.1970.223020","volume":"C19","author":"H Ling","year":"1970","unstructured":"Ling, H.: High-speed computer multiplication using a multiple-bit decoding algorithm. IEEE Trans. Comput. C19, 706\u2013709 (1970)","journal-title":"IEEE Trans. Comput."}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-7470-7_4","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,8]],"date-time":"2019-10-08T06:01:21Z","timestamp":1570514481000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-7470-7_4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789811074691","9789811074707"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-7470-7_4","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2017]]}}}