{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T02:45:40Z","timestamp":1725936340243},"publisher-location":"Singapore","reference-count":15,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811074691"},{"type":"electronic","value":"9789811074707"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-981-10-7470-7_61","type":"book-chapter","created":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T13:17:13Z","timestamp":1513775833000},"page":"646-656","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A 1.8\u00a0V Gain Enhanced Fully Differential Doubly-Recycled Cascode OTA with 100\u00a0dB Gain 200\u00a0MHz UGB in CMOS"],"prefix":"10.1007","author":[{"given":"Antaryami","family":"Panigrahi","sequence":"first","affiliation":[]},{"given":"Abhipsa","family":"Parhi","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,12,21]]},"reference":[{"issue":"6","key":"61_CR1","doi-asserted-by":"crossref","first-page":"1737","DOI":"10.1109\/4.45013","volume":"24","author":"SM Mallya","year":"1989","unstructured":"Mallya, S.M., Nevin, J.H.: Design procedures for a fully differential folded-cascode CMOS operational amplifier. IEEE J. Solid-State Circuits 24(6), 1737\u20131740 (1989)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"3","key":"61_CR2","doi-asserted-by":"crossref","first-page":"204","DOI":"10.1109\/TCSII.2002.1013867","volume":"49","author":"M Das","year":"2002","unstructured":"Das, M.: Improved design criteria of gain-boosted CMOS OTA with high-speed optimizations. IEEE Trans. Circuits Syst. II 49(3), 204\u2013207 (2002)","journal-title":"IEEE Trans. Circuits Syst. II"},{"key":"61_CR3","volume-title":"Design of Analog CMOS Integrated Circuits","author":"B Razavi","year":"2003","unstructured":"Razavi, B.: Design of Analog CMOS Integrated Circuits, 2nd edn. Mc-Graw Hill, New York (2003)","edition":"2"},{"issue":"9","key":"61_CR4","doi-asserted-by":"crossref","first-page":"2535","DOI":"10.1109\/JSSC.2009.2024819","volume":"44","author":"SM Assad","year":"2009","unstructured":"Assad, S.M.: The recycling folded cascode: a general enhancement of the folded cascode amplifier. IEEE J. Solid State Circuits 44(9), 2535\u20132542 (2009)","journal-title":"IEEE J. Solid State Circuits"},{"key":"61_CR5","doi-asserted-by":"crossref","unstructured":"Liu, M., Mak, P.-I., Yan, Z., Martins, R.P.: High-voltage-enabled recycling folded cascode OpAmp for nanoscale CMOS technologies. In: IEEE ISCAS 2011, pp. 33\u201336 (2011)","DOI":"10.1109\/ISCAS.2011.5937494"},{"key":"61_CR6","first-page":"137141","volume":"71","author":"Z Yan","year":"2012","unstructured":"Yan, Z., Mak, P.I., Martins, R.P.: Double recycling technique for folded-cascode OTA. Analog Integr. Circuit Signal Process. 71, 137141 (2012). Springer","journal-title":"Analog Integr. Circuit Signal Process."},{"key":"61_CR7","doi-asserted-by":"crossref","unstructured":"Assaad, R., Silva-Martinez, J.: Enhancing general performance of folded cascode amplifier by recycling current. Electron. Lett. 43(23), 8th November 2007","DOI":"10.1049\/el:20072031"},{"key":"61_CR8","doi-asserted-by":"crossref","unstructured":"Sundararajan, A.D., Rezaul Hasan, S.M.: Quadruply split cross-driven doubly recycled gm-doubling recycled folded cascode for microsensor instrumentation amplifiers. IEEE Trans. Circuits Syst. II: Express Briefs 63(6), June 2016","DOI":"10.1109\/TCSII.2016.2530518"},{"key":"61_CR9","doi-asserted-by":"crossref","unstructured":"Li, Y.L., Han, K.F., Tan, X., Yan, N., Min, H.: Transconductance enhancement method for operational transconductance amplifiers. IET, Electron. Lett. 46(19), 6th September 2010","DOI":"10.1049\/el.2010.1575"},{"issue":"13","key":"61_CR10","doi-asserted-by":"crossref","first-page":"977","DOI":"10.1049\/el.2015.1053","volume":"51","author":"M Akbari","year":"2015","unstructured":"Akbari, M.: Single-stage fully recycling folded cascode OTA for switched-capacitor circuits. IET Electron. Lett. 51(13), 977\u2013979 (2015)","journal-title":"IET Electron. Lett."},{"key":"61_CR11","doi-asserted-by":"crossref","unstructured":"Ahmed, M., Shah, I., Tang, F., Bermak, A.: An improved recycling folded cascode amplifier with gain boosting and phase margin enhancement. In: 2015 IEEE International Symposium on Circuits and Systems, 24\u201327 May 2015, pp. 2473\u20132476 (2015)","DOI":"10.1109\/ISCAS.2015.7169186"},{"key":"61_CR12","doi-asserted-by":"crossref","first-page":"343","DOI":"10.1007\/s10470-015-0535-x","volume":"83","author":"M Akbari","year":"2015","unstructured":"Akbari, M., Hashemipour, O.: Design and analysis of folded cascode OTAs using Gm\/Id methodology based on flicker noise reduction. Analog Integr. Circuits Sig. Process. 83, 343\u2013352 (2015)","journal-title":"Analog Integr. Circuits Sig. Process."},{"key":"61_CR13","doi-asserted-by":"crossref","first-page":"119","DOI":"10.1007\/BF00161305","volume":"1","author":"K Bult","year":"1991","unstructured":"Bult, K., Gelen, G.J.G.M.: The CMOS Gain-Boosting Technique. Analog Integr. Circ. Sig. Process 1, 119\u2013135 (1991)","journal-title":"Analog Integr. Circ. Sig. Process"},{"key":"61_CR14","volume-title":"CMOS Analog Circuit Design","author":"P Allen","year":"2003","unstructured":"Allen, P., Holberg, D.: CMOS Analog Circuit Design, 2nd edn. Oxford University Publications, Oxford (2003)","edition":"2"},{"key":"61_CR15","doi-asserted-by":"crossref","first-page":"1226","DOI":"10.1049\/el:20082200","volume":"44","author":"M Rezaei","year":"2008","unstructured":"Rezaei, M., Zhian-Tabasy, E., Ashtiani, S.J.: Slew rate enhancement method for folded-cascode amplifiers. IET- Electron. Lett. 44, 1226\u20131228 (2008)","journal-title":"IET- Electron. Lett."}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-7470-7_61","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T13:45:51Z","timestamp":1513777551000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-7470-7_61"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789811074691","9789811074707"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-7470-7_61","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2017]]}}}