{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,30]],"date-time":"2025-06-30T04:02:21Z","timestamp":1751256141758,"version":"3.41.0"},"publisher-location":"Singapore","reference-count":7,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811074691"},{"type":"electronic","value":"9789811074707"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-981-10-7470-7_63","type":"book-chapter","created":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T18:17:13Z","timestamp":1513793833000},"page":"667-678","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL\u2019s 0.18\u00a0\u00b5m CMOS Process"],"prefix":"10.1007","author":[{"given":"Munish","family":"Malik","sequence":"first","affiliation":[]},{"given":"Ajay","family":"Kumar","sequence":"additional","affiliation":[]},{"given":"H. S.","family":"Jatana","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,12,21]]},"reference":[{"key":"63_CR1","unstructured":"Draft standard for Low-Voltage differential signals (LVDS) for Scalable Coherent Interface (SCI) Draft 1.3, 27 November 1985"},{"key":"63_CR2","unstructured":"AN-5017 LVDS fundamentals Fairchild Semiconductor application note, December 2000"},{"key":"63_CR3","doi-asserted-by":"crossref","unstructured":"Mandal, G., Mandal, P.: Low-Power LVDS Receiver for 1.3\u00a0Gbps Physical Layer interface. In: ISCAS 2005, vol. 3, pp 2180\u20132183 (2005)","DOI":"10.1109\/ISCAS.2005.1465053"},{"key":"63_CR4","unstructured":"Allen, P.E., Holberg, D.R.: CMOS Analog Circuit Design, 2nd edn. Oxford University Press"},{"key":"63_CR5","volume-title":"The Art of Analog Layout","author":"A Hasting","year":"2001","unstructured":"Hasting, A.: The Art of Analog Layout. Prentice Hall, Upper Saddle River (2001)"},{"issue":"1","key":"63_CR6","first-page":"17","volume":"28","author":"RH Maurer","year":"2008","unstructured":"Maurer, R.H., Fraeman, M.E., Martin, M.N., Roth, D.R.: Harsh Environment: space radiation enviornment, effects, mittigation. Johns Hopkins APL Tech. Dig. 28(1), 17\u201329 (2008)","journal-title":"Johns Hopkins APL Tech. Dig."},{"issue":"4","key":"63_CR7","doi-asserted-by":"crossref","first-page":"706","DOI":"10.1109\/4.913751","volume":"36","author":"A Boni","year":"2001","unstructured":"Boni, A., Pierazzi, A., Vecchi, D.: LVDS I\/O interface for Gb\/s-per-pin operation in 0.35-\u00b5m CMOS. IEEE J. Solid-State Circuits 36(4), 706\u2013711 (2001)","journal-title":"IEEE J. Solid-State Circuits"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-7470-7_63","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,29]],"date-time":"2025-06-29T03:10:11Z","timestamp":1751166611000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-7470-7_63"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789811074691","9789811074707"],"references-count":7,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-7470-7_63","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2017]]}}}