{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T02:45:49Z","timestamp":1725936349647},"publisher-location":"Singapore","reference-count":14,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811074691"},{"type":"electronic","value":"9789811074707"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-981-10-7470-7_71","type":"book-chapter","created":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T18:17:13Z","timestamp":1513793833000},"page":"753-766","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection"],"prefix":"10.1007","author":[{"given":"Binod","family":"Kumar","sequence":"first","affiliation":[]},{"given":"Kanad","family":"Basu","sequence":"additional","affiliation":[]},{"given":"Ankit","family":"Jindal","sequence":"additional","affiliation":[]},{"given":"Brajesh","family":"Pandey","sequence":"additional","affiliation":[]},{"given":"Masahiro","family":"Fujita","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,12,21]]},"reference":[{"key":"71_CR1","doi-asserted-by":"crossref","unstructured":"Park, S.B., Mitra, S.: IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors. In: 45th ACM\/IEEE Design Automation Conference, DAC 2008, pp. 373\u2013378, June 2008","DOI":"10.1145\/1391469.1391569"},{"key":"71_CR2","first-page":"63","volume":"8","author":"R Kuppuswamy","year":"2004","unstructured":"Kuppuswamy, R., DesRosier, P., Feltham, D., Sheikh, R., Thadikaran, P.: Full hold-scan systems in microprocessors: cost\/benefit analysis. Intel Technol. J. 8, 63\u201371 (2004)","journal-title":"Intel Technol. J."},{"issue":"2","key":"71_CR3","doi-asserted-by":"crossref","first-page":"285","DOI":"10.1109\/TCAD.2008.2009158","volume":"28","author":"HF Ko","year":"2009","unstructured":"Ko, H.F., Nicolici, N.: Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2), 285\u2013297 (2009)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"71_CR4","doi-asserted-by":"crossref","unstructured":"Rahmani, K., Mishra, P., Ray, S.: Efficient trace signal selection using augmentation and ILP techniques. In: Fifteenth International Symposium on Quality Electronic Design, pp. 148\u2013155, March 2014","DOI":"10.1109\/ISQED.2014.6783318"},{"issue":"11","key":"71_CR5","doi-asserted-by":"crossref","first-page":"1997","DOI":"10.1109\/TVLSI.2011.2166416","volume":"20","author":"M Gort","year":"2012","unstructured":"Gort, M., Paula, F.M.D., Kuan, J.J.W., Aamodt, T.M., Hu, A.J., Wilton, S.J.E., Yang, J.: Formal-analysis-based trace computation for post-silicon debug. IEEE Trans. Very Large Scale Integr. VLSI Syst. 20(11), 1997\u20132010 (2012)","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"71_CR6","doi-asserted-by":"crossref","unstructured":"Paula, F.M.D., Gort, M., Hu, A.J., Wilton, S.J.E.: Backspace: moving towards reality. In: 2008 Ninth International Workshop on Microprocessor Test and Verification, pp. 49\u201354, December 2008","DOI":"10.1109\/MTV.2008.22"},{"key":"71_CR7","doi-asserted-by":"crossref","unstructured":"Kuan, J.J.W., Aamodt, T.M.: Progressive-backspace: efficient predecessor computation for post-silicon debug. In: 2012 13th International Workshop on Microprocessor Test and Verification (MTV), pp. 70\u201375, December 2012","DOI":"10.1109\/MTV.2012.23"},{"key":"71_CR8","doi-asserted-by":"crossref","unstructured":"de Paula, F.M., Nahir, A., Nevo, Z., Orni, A., Hu, A.J.: Tab-backspace: unlimited-length trace buffers with zero additional on-chip overhead. In: 2011 48th ACM\/EDAC\/IEEE Design Automation Conference (DAC), pp. 411\u2013416, June 2011","DOI":"10.1145\/2024724.2024821"},{"key":"71_CR9","doi-asserted-by":"crossref","unstructured":"Sengupta, D., de Paula, F.M., Hu, A.J., Veneris, A., Ivanov, A.: Lazy suspect-set computation: fault diagnosis for deep electrical bugs. In: Proceedings of the Great Lakes Symposium on VLSI, GLSVLSI 2012, pp. 189\u2013194. ACM, New York (2012)","DOI":"10.1145\/2206781.2206827"},{"key":"71_CR10","doi-asserted-by":"crossref","unstructured":"Kuan, J.J.W., Wilton, S.J.E., Aamodt, T.M.: Accelerating trace computation in post-silicon debug. In: 2010 11th International Symposium on Quality Electronic Design (ISQED), pp. 244\u2013249, March 2010","DOI":"10.1109\/ISQED.2010.5450450"},{"key":"71_CR11","doi-asserted-by":"crossref","unstructured":"Taatizadeh, P., Nicolici, N.: Automated selection of assertions for bit-flip detection during post-silicon validation. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 35(12), 2118\u20132130 (2016)","DOI":"10.1109\/TCAD.2016.2538087"},{"key":"71_CR12","doi-asserted-by":"crossref","unstructured":"Boule, M., Zilic, Z.: Incorporating efficient assertion checkers into hardware emulation. In: 2005 International Conference on Computer Design, pp. 221\u2013228, October 2005","DOI":"10.1109\/ICCD.2005.66"},{"key":"71_CR13","unstructured":"Zhu, C.S., Weissenbacher, G., Malik, S.: Post-silicon fault localisation using maximum satisfiability and backbones. In: International Conference on Formal Methods in Computer-Aided Design, FMCAD 2011, Austin, USA, 30 October\u201302 November, 2011, pp. 63\u201366 (2011)"},{"key":"71_CR14","unstructured":"http:\/\/www.opencores.org\/"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-7470-7_71","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T18:49:25Z","timestamp":1513795765000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-7470-7_71"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789811074691","9789811074707"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-7470-7_71","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2017]]}}}