{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T02:45:51Z","timestamp":1725936351236},"publisher-location":"Singapore","reference-count":9,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811074691"},{"type":"electronic","value":"9789811074707"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-981-10-7470-7_75","type":"book-chapter","created":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T18:17:13Z","timestamp":1513793833000},"page":"805-812","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Faulty TSVs Identification in 3D IC Using Pre-bond Testing"],"prefix":"10.1007","author":[{"given":"Dilip Kumar","family":"Maity","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Surajit Kumar","family":"Roy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chandan","family":"Giri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,12,21]]},"reference":[{"issue":"6","key":"75_CR1","doi-asserted-by":"crossref","first-page":"498","DOI":"10.1109\/MDT.2005.136","volume":"22","author":"WR Davis","year":"2005","unstructured":"Davis, W.R., et al.: Demystifying 3DICs: the pros and cons of going vertical. IEEE Des. Test Comput. 22(6), 498\u2013510 (2005)","journal-title":"IEEE Des. Test Comput."},{"issue":"6","key":"75_CR2","doi-asserted-by":"crossref","first-page":"26","DOI":"10.1109\/MDT.2009.125","volume":"26","author":"H Lee","year":"2009","unstructured":"Lee, H., Chakrabarty, K.: Test challenges for 3D integrated circuits. IEEE Des. Test Comput. 26(6), 26\u201335 (2009)","journal-title":"IEEE Des. Test Comput."},{"key":"75_CR3","unstructured":"Chen, H., Shih, J., Li, S.W., Lin, H.C., Wang, M., Peng, C.: Electrical tests for Three-Dimensional ICs (3DICs) with TSVs. In: International Test Conference 3D-Test Workshop, pp. 1\u20136 (2010)"},{"key":"75_CR4","doi-asserted-by":"crossref","unstructured":"Noia, B., Chakrabarty, K.: Pre-bond probing of TSVs in 3D stacked ICs. In: Proceedings of IEEE International Test Conference, pp. 1\u201310 (2011)","DOI":"10.1109\/TEST.2011.6139179"},{"key":"75_CR5","doi-asserted-by":"crossref","unstructured":"Noia, B., Chakrabarty, K.: Identification of defective TSVs in pre-bond testing of 3D ICs. In: Proceedings of IEEE Asian Test Symposium (ATS), pp. 187\u2013194 (2011)","DOI":"10.1109\/ATS.2011.57"},{"key":"75_CR6","doi-asserted-by":"crossref","unstructured":"Zhang, B., Agrawal, V.D.: Diagnostic tests for pre-bond TSV defects. In: Proceedings of IEEE International Conference on VLSI Design, pp. 387\u2013392 (2014)","DOI":"10.1109\/ICCD.2014.6974680"},{"key":"75_CR7","doi-asserted-by":"crossref","unstructured":"Roy, S.K., Chatterjee, S., Giri, C.: Identifying faulty TSVs in 3D stacked IC during pre-bond testing. In: Proceedings of IEEE International Symposium on Electronic System Design (ISED), pp. 162\u2013166 (2012)","DOI":"10.1109\/ISED.2012.49"},{"key":"75_CR8","doi-asserted-by":"crossref","unstructured":"Roy, S.K., Chatterjee, S., Giri, C., Rahaman, H.: Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing. In: Proceedings of International 3D Systems Integration Conference (3DIC), pp. 1\u20136 (2013)","DOI":"10.1109\/3DIC.2013.6702339"},{"key":"75_CR9","doi-asserted-by":"crossref","unstructured":"Zhang, B., Agrawal, V.D.: An optimal probing method of pre-bond TSV fault identification for 3D stacked ICs. In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (2014)","DOI":"10.1109\/S3S.2014.7028201"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-7470-7_75","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,8]],"date-time":"2019-10-08T10:05:14Z","timestamp":1570529114000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-7470-7_75"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789811074691","9789811074707"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-7470-7_75","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2017]]}}}